公开(公告)号：US20170365659A1

公开(公告)日：2017-12-21

申请号：US15697529

申请日：2017-09-07

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Darsen D. Lu ,  Xin Miao ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

公开(公告)号：US20170162650A1

公开(公告)日：2017-06-08

申请号：US14957809

申请日：2015-12-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Darsen D. Lu ,  Xin Miao ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

公开(公告)号：US09583492B2

公开(公告)日：2017-02-28

申请号：US15069557

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/308 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

公开(公告)号：US09553173B1

公开(公告)日：2017-01-24

申请号：US14962082

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Chung H. Lam ,  Chung-hsun Lin ,  Darsen D. Lu ,  Philip J. Oldiges

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/02 ,  H01L29/08 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795

Abstract: A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged on the doped source layer, a fin arranged on the insulator layer, a source region extension portion extending from the doped source layer and through the fin, a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion, a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.

公开(公告)号：US09548386B1

公开(公告)日：2017-01-17

申请号：US14840960

申请日：2015-08-31

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L29/78 ,  H01L21/32 ,  H01L21/02 ,  H01L21/308 ,  H01L21/324 ,  H01L21/306 ,  H01L21/311 ,  H01L21/283 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/785

Abstract: A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.

Abstract translation: 一种形成半导体结构的方法，该半导体结构包括从衬底的第一部分和nFET器件区域向上延伸的紧张应变的硅鳍，以及从衬底的第二部分向上延伸的SiGe鳍结构以及pFET器件区域 。 根据本申请，SiGe鳍结构从底部到顶部包括松弛的下部SiGe鳍和上部SiGe鳍，其中上部SiGe鳍被压缩应变并且具有大于锗的锗含量 含量较低的SiGe鳍。

公开(公告)号：US09548213B2

公开(公告)日：2017-01-17

申请号：US14189294

申请日：2014-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

Abstract translation: 一种形成翅片结构的方法，其包括从体半导体衬底形成多个翅片结构，并在所述多个翅片结构中的每个翅片结构的侧壁上形成电介质间隔物。 在电介质间隔物的侧壁上形成半导体衬垫。 在相邻翅片结构之间的空间中形成介电填料。 存在于电介质隔板的下表面下方的半导体间隔物和翅片结构的一部分被氧化。 氧化翅片结构的基部产生第一应变并且氧化半导体间隔物产生与第一应变相反的第二应变。

公开(公告)号：US20160233315A1

公开(公告)日：2016-08-11

申请号：US15134960

申请日：2016-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/66 ,  H01L21/324 ,  H01L29/10 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

公开(公告)号：US20160133697A1

公开(公告)日：2016-05-12

申请号：US14980210

申请日：2015-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/0638 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type.

公开(公告)号：US09299618B1

公开(公告)日：2016-03-29

申请号：US14495342

申请日：2014-09-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Abstract translation: 提供了包含通过外延半导体堆叠与下层体硅衬底隔离的半导体鳍片的非平面半导体结构。 提供隔离的外延半导体材料堆叠包括从底部到顶部的包含至少一种导电类型的不同于形成半导体鳍片的特定器件区域的导电类型的掺杂剂的半导体冲击穿通停止器，以及 不含n型或p型掺杂剂的半导体扩散阻挡层。

公开(公告)号：US09276113B2

公开(公告)日：2016-03-01

申请号：US14202525

申请日：2014-03-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L29/0638 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type.

Abstract translation: 一种形成半导体器件的方法，包括在鳍结构上形成栅极结构并蚀刻鳍结构的源极和漏极区域以提供凹陷表面。 第一半导体层形成在鳍状结构的凹入表面上，该第一半导体层被掺杂到第一导电类型。 在第一半导体层上形成漏电阻层。 在漏电阻层上形成第二半导体层。 第二半导体层被掺杂到第二导电类型。