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    RESISTIVE MEMORY SENSING
    52.
    发明申请
    RESISTIVE MEMORY SENSING 有权
    电阻记忆感应

    公开(公告)号：US20140169066A1

    公开(公告)日：2014-06-19

    申请号：US13921951

    申请日：2013-06-19

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

    Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

    Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。

    Memory module multiple port buffer techniques
    53.
    发明授权
    Memory module multiple port buffer techniques 有权

    公开(公告)号：US12300349B2

    公开(公告)日：2025-05-13

    申请号：US18087328

    申请日：2022-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

    IPC: G11C7/10 ,  G11C7/22

    Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

    SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES
    54.
    发明申请
    SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES 有权

    公开(公告)号：US20250149108A1

    公开(公告)日：2025-05-08

    申请号：US18775981

    申请日：2024-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Sai Krishna Mylavarapu ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Brent Keeth ,  Lance P. Johnson ,  Amy Rae Griffin

    IPC: G11C29/00 ,  G11C29/52

    Abstract: Methods, systems, and devices for sparing techniques in stacked memory architectures are described. A memory system may implement a stacked memory architecture that includes a set of array dies stacked along a direction and a logic die coupled with the set of array dies. Each array die may include one or more memory arrays accessible using one or more first interface blocks of the array die. To support sparing, the memory system may remap access from one or more first memory arrays of the set of array dies to one or more second memory arrays of the set of array dies. Logic circuitry of the logic die may be operable to perform the remapping in accordance with one or more levels of granularity, such as at a die level, channel level, pseudo-channel level, bank level, or a combination thereof.

    DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES
    55.
    发明申请
    DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES 有权

    公开(公告)号：US20250077353A1

    公开(公告)日：2025-03-06

    申请号：US18762284

    申请日：2024-07-02

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Ameen D. Akel ,  Shivasankar Gunasekaran ,  Sai Krishna Mylavarapu

    IPC: G06F11/10

    Abstract: Methods, systems, and devices for data protection techniques in stacked memory architectures are described. A memory system having a stacked memory architecture may include error correction information associated with a data set that includes multiple data segments stored across multiple memory arrays and, in some examples, multiple dies of the memory system. As part of a write operation for a first data segment of a data set, the memory system may retrieve the remaining data segments of the data set and calculate error correction information using the first data segment and the remaining data segments. As part of a read operation for a second data segment of the data set, the memory system may retrieve each data segment of the data set and perform an error correction operation on the data set using the error correction information.

    DATA PATH SIGNAL AMPLIFICATION IN COUPLED SEMICONDUCTOR SYSTEMS
    56.
    发明公开
    DATA PATH SIGNAL AMPLIFICATION IN COUPLED SEMICONDUCTOR SYSTEMS 审中-公开

    公开(公告)号：US20240355371A1

    公开(公告)日：2024-10-24

    申请号：US18607033

    申请日：2024-03-15

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

    IPC: G11C7/10 ,  G11C7/22 ,  G11C29/52

    CPC classification number: G11C7/1069 ,  G11C7/222 ,  G11C29/52

    Abstract: Methods, systems, and devices for data path signal amplification in coupled semiconductor systems are described. A semiconductor system may implement a first die including memory arrays and a second die including a host interface. The first die may include a first portion of a data path between the memory arrays and the host interface, including a first portion of data path signal amplification circuitry. The second die may include a second portion of the data path, including a second portion of data path signal amplification circuitry. The semiconductor system may implement fine-pitch interconnection between dies to support a relatively greater quantity of signal paths of the data path which, in some examples, may support reducing or eliminating serialization/deserialization circuitry associated with coarser interconnection. In some implementations, a semiconductor system may implement a switching component operable to switch between data paths having different amplification configurations of the dies.

    MEMORY WITH PARALLEL MAIN AND TEST INTERFACES
    59.
    发明公开
    MEMORY WITH PARALLEL MAIN AND TEST INTERFACES 审中-公开

    公开(公告)号：US20240071556A1

    公开(公告)日：2024-02-29

    申请号：US17821676

    申请日：2022-08-23

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson ,  Kunal R. Parekh ,  Brent Keeth ,  Eiichi Nakano ,  Amy Rae Griffin

    IPC: G11C29/56 ,  G11C7/10

    CPC classification number: G11C29/56004 ,  G11C7/1039 ,  G11C29/56016 ,  G11C2029/5602

    Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

    MEMORY DEVICE INTERFACE AND METHOD
    60.
    发明公开
    MEMORY DEVICE INTERFACE AND METHOD 审中-公开

    公开(公告)号：US20230376235A1

    公开(公告)日：2023-11-23

    申请号：US18138527

    申请日：2023-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth

    IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04

    CPC classification number: G06F3/0655 ,  G06F3/0679 ,  G06F3/0604 ,  G11C7/1006 ,  G11C5/04

    Abstract: Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

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