公开(公告)号：US20240321349A1

公开(公告)日：2024-09-26

申请号：US18622033

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71

Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

公开(公告)号：US20240237360A1

公开(公告)日：2024-07-11

申请号：US18617466

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  G11C13/0004 ,  G11C13/003 ,  H10N70/231 ,  G11C2213/71

Abstract: An array of memory cells in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. The connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels.

公开(公告)号：US20240212752A1

公开(公告)日：2024-06-27

申请号：US18518126

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Michele Maria Venturini

IPC: G11C13/04 ,  H03K17/687

CPC classification number: G11C13/042 ,  H03K17/687

Abstract: A detection circuit may be configured to receive an input signal indicative of a data state and to detect the data state using charge sharing between two capacitors to achieve detection with threshold compensation . The detection circuit may include semi-latch circuitry and boosting circuitry to expedite the detection, thereby achieving high speed at low power consumption and low circuit size.

公开(公告)号：US20240212744A1

公开(公告)日：2024-06-27

申请号：US18537685

申请日：2023-12-12

Applicant: Micron Technology, Inc.

Inventor： Umberto di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device uses an architecture having a precharge transistor in parallel with a cascode transistor. The precharge transistor (e.g., a p-channel device) performs precharging of a bitline to a fixed constant voltage in preparation for sensing a memory cell. The cascode transistor (e.g., an n-channel device) is used to determine the voltage of the bitline during sensing and discharges a sensing node if the memory cell switches (e.g., snaps). The sensing node is coupled to an input of a detector that determines the logic state of the memory cell.

公开(公告)号：US20240194272A1

公开(公告)日：2024-06-13

申请号：US18586134

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C29/52

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C29/52

Abstract: The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.

公开(公告)号：US20240134802A1

公开(公告)日：2024-04-25

申请号：US17972493

申请日：2022-10-23

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC: G06F12/0891

CPC classification number: G06F12/0891 ,  G06F2212/305

Abstract: Systems, methods, and apparatus for a memory device that stores a scrub list in a cache used to reduce data traffic to and from a memory array. In one approach, the cache merges the scrub list with cache data. Data in the scrub list can be identified and distinguished from the cache data by adding a one-bit scrub flag to each data entry in the merged cache. In this merged approach, the cache data shares the same memory as the scrub list. Read data that has an error is saved temporarily in this merged cache until the correct value for the data is written back into the memory array.

公开(公告)号：US11915740B2

公开(公告)日：2024-02-27

申请号：US17686240

申请日：2022-03-03

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC: G11C8/00 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093

CPC classification number: G11C11/4082 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093

Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

公开(公告)号：US20230395147A1

公开(公告)日：2023-12-07

申请号：US17855483

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Umberto di Vincenzo ,  Ferdinando Bedeschi ,  Christian Marc Benoit Caillat

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/71

Abstract: Systems, methods, and apparatus for a memory device that uses multiple groups of pattern cells to select a voltage for reading memory cells. In one approach, a controller applies different magnitude levels of voltages to each of the groups of pattern cells. The controller determines which of the groups have pattern cells that first switch (e.g., switch at the lowest magnitude of applied voltage). Based on identifying the first group to switch, the controller selects a read voltage. The selected read voltage is used to read data cells (e.g., corresponding to a codeword).

公开(公告)号：US20230307041A1

公开(公告)日：2023-09-28

申请号：US17655957

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71

Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

公开(公告)号：US20230282301A1

公开(公告)日：2023-09-07

申请号：US18112307

申请日：2023-02-21

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/14 ,  G11C29/20 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C7/14 ,  G11C29/20 ,  G11C29/12005

Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.