公开(公告)号：US09748474B2

公开(公告)日：2017-08-29

申请号：US14524322

申请日：2014-10-27

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal R. Parekh

IPC: H01L47/00 ,  H01L45/00 ,  H01L21/033 ,  H01L21/768 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L21/0337 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/2472 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

公开(公告)号：US09721655B2

公开(公告)日：2017-08-01

申请号：US13906964

申请日：2013-05-31

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: H01L47/00 ,  G11C13/00 ,  G11C11/56 ,  H01L27/102 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0009 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2213/56 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

Abstract: Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.

公开(公告)号：US20170140806A1

公开(公告)日：2017-05-18

申请号：US15421204

申请日：2017-01-31

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/66007 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

公开(公告)号：US09627611B2

公开(公告)日：2017-04-18

申请号：US13683418

申请日：2012-11-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US09620709B2

公开(公告)日：2017-04-11

申请号：US15048746

申请日：2016-02-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Jian Li

IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141

Abstract: Embodiments disclosed herein may relate to heating a phase change memory (PCM) cell.

公开(公告)号：US20160276028A1

公开(公告)日：2016-09-22

申请号：US15165800

申请日：2016-05-26

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Jun Liu

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

Abstract translation: 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

公开(公告)号：US09424920B2

公开(公告)日：2016-08-23

申请号：US14982810

申请日：2015-12-29

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/165

Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

公开(公告)号：US09412936B2

公开(公告)日：2016-08-09

申请号：US14854212

申请日：2015-09-15

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  John K. Zahurak

IPC: H01L29/06 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.

公开(公告)号：US20160190438A1

公开(公告)日：2016-06-30

申请号：US15063238

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract translation: 一些实施例包括形成存储器单元的方法。 这样的方法可以包括形成第一电极，第二电极和直接接触第一和第二电极的存储元件。 存储元件的形成可以包括通过存储元件的第一部分形成与第一电极隔离的存储元件的可编程部分，并通过存储元件的第二部分与第二电极隔离。 描述其他实施例。

公开(公告)号：US09281478B2

公开(公告)日：2016-03-08

申请号：US14458804

申请日：2014-08-13

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L21/00 ,  H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract translation: 一些实施例包括形成存储器单元的方法。 这样的方法可以包括形成第一电极，第二电极和直接接触第一和第二电极的存储元件。 存储元件的形成可以包括通过存储元件的第一部分形成与第一电极隔离的存储元件的可编程部分，并通过存储元件的第二部分与第二电极隔离。 描述其他实施例。