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    APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES
    53.
    发明申请
    APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES 有权
    使用编程到不同状态的细胞的装置和方法

    公开(公告)号：US20160104533A1

    公开(公告)日：2016-04-14

    申请号：US14509953

    申请日：2014-10-08

    Applicant: Micron Technology, Inc.

    Inventor： TORU TANZAWA ,  Aaron Yip

    IPC: G11C16/04 ,  G11C16/10

    CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

    Abstract: Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A. plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations.

    Abstract translation: 描述了用于降低电容负载的装置和方法。 示例性装置可以包括存储器块的多个存储器子块。 多个字线可以与多个子块相关联。 字线可以进一步与子块内的多个字符串相关联。 字线的子集可以是虚拟字线。 虚拟字线的单元可以被编程为多个状态。 可以将状态配置为在某些存储器操作期间停用和/或浮动子块中未选择的字符串。

    SENSE OPERATION FLAGS IN A MEMORY DEVICE
    56.
    发明申请
    SENSE OPERATION FLAGS IN A MEMORY DEVICE 有权
    在存储器中识别操作标志

    公开(公告)号：US20150363313A1

    公开(公告)日：2015-12-17

    申请号：US14833175

    申请日：2015-08-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC: G06F12/08 ,  G06F13/28 ,  G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

    Abstract translation: 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

    SINGLE CHECK MEMORY DEVICES AND METHODS
    57.
    发明申请
    SINGLE CHECK MEMORY DEVICES AND METHODS 有权
    单次检查记忆装置和方法

    公开(公告)号：US20140351663A1

    公开(公告)日：2014-11-27

    申请号：US14263736

    申请日：2014-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Vishal Sarin ,  Aaron Yip ,  Tomoharu Tanaka

    IPC: G11C29/50

    CPC classification number: G11C29/50004 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2029/5004 ,  G11C2211/5621

    Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.

    Abstract translation: 显示了存储器件和操作存储器件的方法。 所描述的配置包括在编程脉冲之间执行单次检查以确定相对于期望的基准电压的阈值电压的电路。 在一个示例中，基准电压用于改变所选存储单元的编程速度。

    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
    58.
    发明申请
    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES 有权

    公开(公告)号：US20250078940A1

    公开(公告)日：2025-03-06

    申请号：US18794538

    申请日：2024-08-05

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24

    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
    60.
    发明公开
    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20230360710A1

    公开(公告)日：2023-11-09

    申请号：US18195181

    申请日：2023-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/24 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24

    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

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