公开(公告)号：US10734395B2

公开(公告)日：2020-08-04

申请号：US16663068

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10727242B2

公开(公告)日：2020-07-28

申请号：US16372563

申请日：2019-04-02

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Matthew Park ,  Joseph Neil Greeley ,  Chet E. Carter ,  Martin C. Roberts ,  Indra V. Chary ,  Vinayak Shamanna ,  Ryan Meyer ,  Paolo Tessariol

IPC: H01L27/11 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

公开(公告)号：US20200161332A1

公开(公告)日：2020-05-21

申请号：US16751116

申请日：2020-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11556 ,  H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L29/10 ,  H01L21/3213

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US20200075630A1

公开(公告)日：2020-03-05

申请号：US16674823

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L27/11529 ,  H01L27/1157 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L21/28

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US10283524B1

公开(公告)日：2019-05-07

申请号：US15848612

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US20190051823A1

公开(公告)日：2019-02-14

申请号：US16160518

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Timothy A. Quick ,  Eugene P. Marsh ,  Stefan Uhlenbrock ,  Chet E. Carter ,  Scott E. Sills

IPC: H01L45/00

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

公开(公告)号：US10014309B2

公开(公告)日：2018-07-03

申请号：US15231950

申请日：2016-08-09

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Matthew Park ,  Joseph Neil Greeley ,  Chet E. Carter ,  Martin C. Roberts ,  Indra V. Chary ,  Vinayak Shamanna ,  Ryan Meyer ,  Paolo Tessariol

IPC: H01L21/336 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

公开(公告)号：US09755035B2

公开(公告)日：2017-09-05

申请号：US14080629

申请日：2013-11-14

Applicant: Micron Technology, Inc.

Inventor： Andrey V. Zagrebelny ,  Chet E. Carter ,  Andrew D. Carswell

IPC: H01L29/45 ,  H01L23/532 ,  H01L21/283 ,  H01L21/768 ,  H01L21/321 ,  H01L45/00

CPC classification number: H01L29/45 ,  H01L21/283 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L23/53242 ,  H01L23/53295 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide. Chemical-mechanical polishing is utilized to form a planarized surface extending across the platinum-containing material and the metal oxide.

公开(公告)号：US20140103285A1

公开(公告)日：2014-04-17

申请号：US14137477

申请日：2013-12-20

Applicant: Micron Technology, Inc.

Inventor： Andrey V. Zagrebelny ,  Chet E. Carter

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L21/3212 ,  H01L21/7684 ,  H01L23/53242 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/085 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide.

Abstract translation: 一些实施方案包括图案化含铂材料的方法。 可以形成开口以延伸到氧化物中。 含铂的材料可以形成在氧化物的上表面上并且直接抵靠氧化物的上表面，并且在开口内形成。 开口内的含铂材料可以是具有侧面周边的塞子。 插塞的侧边缘可以直接抵靠氧化物。 可以对含铂材料进行抛光以从氧化物的上表面上除去含铂材料。 抛光可能使氧化物中的含铂材料分层，并且可以从氧化物上除去含铂材料，相对于含铂材料相对于氧化物的选择性至少约为5:1。 一些实施例包括形成存储器单元的方法。 一些实施例包括在氧化物的开口内并且直接抵靠氧化物的含铂材料的集成电路。

公开(公告)号：US20250142820A1

公开(公告)日：2025-05-01

申请号：US19009060

申请日：2025-01-03

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.