公开(公告)号：US06908840B2

公开(公告)日：2005-06-21

申请号：US10640096

申请日：2003-08-13

申请人： Tse-Yao Huang ,  Yi-Nan Chen

发明人： Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76847 ,  H01L27/10873 ,  H01L27/10888

摘要： A method of filling a bit line contact via. The method includes providing a substrate having a transistor, with a gate electrode, drain region, and source region, on the substrate, forming a first barrier layer overlying the sidewall of the gate electrode, drain region, and source region, forming a first conductive layer overlying the first barrier layer, removing the first barrier layer and first conductive layer above the source region, forming an insulating barrier layer overlying the substrate, forming a first dielectric layer overlying the insulating barrier layer above the source region, forming a second dielectric layer overlying the substrate, forming a via through the second dielectric layer and the insulative barrier layer, exposing the first conductive layer, forming a second barrier layer overlying the surface of the via, and filling the via with a second conductive layer.

摘要翻译： 填充位线接触通孔的方法。 该方法包括在衬底上提供具有栅电极，漏极区和源极区的晶体管的衬底，形成覆盖在栅电极，漏区和源极区的侧壁上的第一势垒层，形成第一导电 层，覆盖第一阻挡层，去除源极区上方的第一阻挡层和第一导电层，形成覆盖在衬底上的绝缘阻挡层，形成覆盖在源区上方的绝缘阻挡层的第一介电层，形成第二介电层 覆盖衬底，通过第二电介质层和绝缘阻挡层形成通孔，暴露第一导电层，形成覆盖通孔表面的第二阻挡层，并用第二导电层填充通孔。

公开(公告)号：US20050042871A1

公开(公告)日：2005-02-24

申请号：US10727790

申请日：2003-12-04

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： C03C15/00 ,  H01L21/033 ,  H01L21/308 ,  H01L21/8242 ,  B32B17/06 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US06737334B2

公开(公告)日：2004-05-18

申请号：US10268522

申请日：2002-10-09

申请人： Tzu-En Ho ,  Chang Rong Wu ,  Yi-Nan Chen

发明人： Tzu-En Ho ,  Chang Rong Wu ,  Yi-Nan Chen

IPC分类号： H01L218242

CPC分类号： H01L21/76224 ,  H01L21/31111

摘要： A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.

摘要翻译： 一种制造用于半导体器件的STI的方法。 该方法包括以下步骤。 在半导体衬底上形成沟槽，在沟槽的底部和侧壁上形成衬里氧化物，然后在衬里氧化物上形成衬里氮化物。 第一氧化物层通过高密度等离子体化学气相沉积沉积在沟槽中。 将第一氧化物层喷雾刻蚀至预定深度，其中喷雾蚀刻溶液的配方为HF / H 2 SO 4 = 0.3〜0.4。 沉积第二氧化物层以通过高密度等离子体化学气相沉积填充沟槽以形成浅沟槽隔离结构。

公开(公告)号：US6055743A

公开(公告)日：2000-05-02

申请号：US9158

申请日：1998-01-20

申请人： Yi-Nan Chen ,  Wen-Chi Hsu

发明人： Yi-Nan Chen ,  Wen-Chi Hsu

IPC分类号： H01L21/304 ,  H01L21/00 ,  F26B3/00

CPC分类号： H01L21/67028

摘要： A method and an apparatus for drying a semiconductor wafer. The semiconductor wafer is first dipped in a liquid with a volatility higher than water and which is miscible with water. The dipped semiconductor wafer is then delivered in an IPA dryer to carry out the drying process. The drying process includes evaporating isopropyl alcohol to obtain a vapor and condensing the IPA vapor on the surface of the semiconductor wafer. The IPA is heated and vaporized by a hot plate disposed at the bottom of the IPA dryer. The condenser is mounted on the inner peripheral surface of the IPA dryer and surrounds the semiconductor wafer, which is supported by a holder.

摘要翻译： 一种用于干燥半导体晶片的方法和装置。 首先将半导体晶片浸入挥发性高于水并与水混溶的液体中。 然后将浸渍的半导体晶片在IPA干燥器中输送以进行干燥过程。 干燥过程包括蒸发异丙醇以获得蒸汽并将半导体晶片表面上的IPA蒸气冷凝。 IPA由设置在IPA干燥器底部的热板加热和蒸发。 冷凝器安装在IPA干燥器的内周表面上，并且围绕由保持器支撑的半导体晶片。

公开(公告)号：US08912595B2

公开(公告)日：2014-12-16

申请号：US13106852

申请日：2011-05-12

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/308

CPC分类号： H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.

摘要翻译： 公开了一种沟槽MOS结构。 沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 沟槽栅极部分地设置在掺杂区域中。 沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。 两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

公开(公告)号：US08816715B2

公开(公告)日：2014-08-26

申请号：US13105913

申请日：2011-05-12

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L21/66 ,  G01R31/28

CPC分类号： H01L22/34 ,  G01R31/02 ,  G01R31/26 ,  G01R31/2644 ,  G01R31/2831

摘要： A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

摘要翻译： 公开了MOS测试结构。 划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。 外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。 第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。 导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接 到外延层，使得测试通孔能够一起测试外延层和衬底。

公开(公告)号：US08692318B2

公开(公告)日：2014-04-08

申请号：US13104924

申请日：2011-05-10

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

摘要： A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

摘要翻译： 提供沟槽MOS结构。 沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 沟槽设置在外延层中。 栅极隔离覆盖沟槽的内壁。 沟槽栅设置在沟槽中并且具有第一导电类型。 保护环具有第二导电类型并且设置在外延层内。 加强结构具有电绝缘材料并且设置在保护环内。

公开(公告)号：US08458842B2

公开(公告)日：2013-06-11

申请号：US13104964

申请日：2011-05-10

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B08B3/02

CPC分类号： H01L21/67051 ,  H01L21/02052 ,  H01L21/67046

摘要： A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member.

摘要翻译： CMP后晶片清洗装置包括：腔室; 多个辊子，适于在所述腔室内保持和旋转晶片; 至少一个刷子，适于擦拭要清洁的晶片的表面; 以及适于将液体喷射在晶片上的液体喷射装置，所述液体喷射装置包括通过接头构件连接在一起的两个喷射杆。

公开(公告)号：US08394721B2

公开(公告)日：2013-03-12

申请号：US13104986

申请日：2011-05-11

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/311

CPC分类号： H01L27/0203 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

摘要翻译： 一种用于获得现有集成电路的布局设计的方法，其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面，并且获得倾斜抛光表面的一个或多个图像。 图像可以直接重叠，或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。

公开(公告)号：US20130052820A1

公开(公告)日：2013-02-28

申请号：US13214244

申请日：2011-08-22

申请人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/28

CPC分类号： H01L21/321 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76876 ,  H01L21/76885

摘要： A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.

摘要翻译： 提供形成导电图案的方法。 在底层上形成接种层。 通过使用能量射线，对接种层的表面的一部分进行照射处理。 因此，接种层包括多个照射区域和多个未照射区域。 对接种层的照射区域进行转化处理。 进行选择性生长处理，以在接种层的每个未照射区域上形成导电图案。 去除接种层的照射区域，使得导电图案彼此绝缘。