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公开(公告)号：US06562717B1
公开(公告)日：2003-05-13
申请号：US09679874
申请日：2000-10-05
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/66545
摘要： A method of manufacturing a semiconductor device includes providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; and forming first and second nickel silicide layer respectively disposed on the source/drain regions and the gate electrode. The nickel silicide layer over the gate electrode can be thicker than the nickel silicide layer over the source/drain regions. A semiconductor device formed from the method is also disclosed.
摘要翻译： 一种制造半导体器件的方法包括：在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 以及形成分别设置在源极/漏极区域和栅极电极上的第一和第二硅化镍层。 栅电极上的硅化镍层可以比源/漏区上的硅化镍层厚。 还公开了由该方法形成的半导体器件。
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公开(公告)号：US06555453B1
公开(公告)日：2003-04-29
申请号：US10058219
申请日：2002-01-29
申请人： Qi Xiang , Christy Mei-Chu Woo , George J. Kluth
发明人： Qi Xiang , Christy Mei-Chu Woo , George J. Kluth
IPC分类号： H01L2128
CPC分类号： H01L29/66507 , H01L21/2257 , H01L21/28097 , H01L21/28518 , H01L29/41783 , H01L29/4975 , H01L29/6659
摘要： Semiconductor devices having fully metal silicided gate electrodes, and methods for making the same, are disclosed. The devices have shallow S/D extensions with depths of less than about 500 Å. The methods for making the subject semiconductor devices employ diffusion of dopant from metal suicides to form shallow S/D extensions, followed by high energy implantation and activation, and metal silicidation to form S/D junctions having metal silicide connect regions and a fully metal silicided electrode.
摘要翻译： 公开了具有完全金属硅化物栅电极的半导体器件及其制造方法。 这些器件具有深度小于约500的浅的S / D延伸。 制造本发明的半导体器件的方法是使用掺杂剂从金属硅化物扩散以形成浅的S / D扩展，接着是高能量注入和激活，以及金属硅化以形成具有金属硅化物连接区域和全金属硅化物的S / D结 电极。
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公开(公告)号：US06541860B1
公开(公告)日：2003-04-01
申请号：US09875457
申请日：2001-06-05
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76873 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and a method for manufacture thereof are provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. An opening is formed in the dielectric layer. A barrier layer with an alloying element is deposited to line the opening in the dielectric layer. A conductor core is deposited on the barrier layer to fill the opening and connect to the semiconductor device. The conductor core is annealed causing migration of the alloy element into the conductor core.
摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 在半导体衬底上形成器件电介质层。 在电介质层中形成开口。 沉积具有合金元素的阻挡层以使介电层中的开口线对齐。 导体芯沉积在阻挡层上以填充开口并连接到半导体器件。 导体芯退火，导致合金元件迁移到导体芯中。
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54.发明授权Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer 失效在无电镀铜种子层的低k互连上形成低电阻势垒的方法公开(公告)号：US06509267B1
公开(公告)日：2003-01-21
申请号：US09884058
申请日：2001-06-20
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76832 , H01L21/76846 , H01L21/76873
摘要： A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate. The second metal layer serves as a nucleation step for electrolessly plating a copper seed layer.
摘要翻译： 用于形成金属互连结构的方法在电介质层的图案化开口内提供诸如氮化物之类的阻挡材料的共形层。 在将开口蚀刻到电介质层上之后，阻挡材料沉积，停止在扩散阻挡层上。 诸如钽的金属阻挡材料的第一层被共形沉积在阻挡材料上。 执行定向蚀刻，其去除水平氮化物和钽，留下图案化开口的侧壁上的氮化物和钽。 阻挡材料在覆盖导电材料的扩散阻挡层的蚀刻期间以及在随后的溅射蚀刻清洁期间防止介电层从导电材料（例如铜）中的污染。 薄的第二金属层被共形沉积，并且在开口的侧壁上形成合适的阻挡层，同时在第二金属层和下面的基底之间提供低的接触电阻。 第二金属层用作无机电镀铜籽晶层的成核步骤。
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55.发明授权Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability 有权利用退火增强或修复种子层以提高铜互连的可靠性公开(公告)号：US06506668B1
公开(公告)日：2003-01-14
申请号：US09887148
申请日：2001-06-22
IPC分类号： H01L213205
CPC分类号： H01L21/76843 , C25D7/123 , H01L21/76858 , H01L21/76864 , H01L21/76868 , H01L21/76873 , H01L21/76877 , H01L21/76883 , H01L2221/1089
摘要： A method of forming interconnects on a semiconductor chip is disclosed which comprises the steps of: depositing a barrier layer and a copper seed layer on the semiconductor chip; depositing on the copper seed layer an enhancement layer; annealing the semiconductor chip a first time after the copper seed layer and the enhancement layer are deposited to form an annealed layer; electroplating a copper layer on the semiconductor chip; and annealing the semiconductor chip a second time after the copper layer is deposited on the annealed layer to form an annealed copper conductive layer.
摘要翻译： 公开了一种在半导体芯片上形成互连的方法，其包括以下步骤：在半导体芯片上沉积阻挡层和铜籽晶层; 在铜籽晶层上沉积增强层; 在沉积铜籽晶层和增强层之后，首先退火半导体芯片，形成退火层; 在半导体芯片上电镀铜层; 并且在铜层沉积在退火层上之后第二次对半导体芯片退火以形成退火的铜导电层。
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56.发明授权公开(公告)号：US06402909B1
公开(公告)日：2002-06-11
申请号：US09678504
申请日：2000-10-02
IPC分类号： C25D1700
CPC分类号： C25D17/001 , C25D7/123 , Y10S204/07
摘要： An electroplating system is provided for semiconductor wafers which include a plating chamber having a consumable shielded secondary anode shielded by an inert anode from a semiconductor wafer connector. For a copper plating system the plating chamber has a consumable copper shielded anode shielded by an inert platinum anode from a semiconductor wafer connector.
摘要翻译： 为半导体晶片提供电镀系统，其包括具有由半导体晶片连接器被惰性阳极屏蔽的消耗屏蔽二次阳极的电镀室。 对于镀铜系统，电镀室具有由半导体晶片连接器的惰性铂阳极屏蔽的消耗铜屏蔽阳极。
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57.发明授权Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films 失效化学机械抛光浆料配方及钨钛薄膜的制备方法
公开(公告)号：US5916855A
公开(公告)日：1999-06-29
申请号：US829704
申请日：1997-03-26
IPC分类号： C09G1/02 , C09K3/14 , H01L21/321 , H01L21/3105 , H01L21/306
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/3212
摘要： A polishing slurry composition and its method of making for planarization of silicon semiconductor wafers by chemical mechanical polishing of the wafer. A slurry formulation utilizing a ferric salt tungsten oxidizer, an ammonium persulfate titanium oxidizer, a fatty acid suspension agent, alumina particles with a small diameter and tight diameter range, coated with a solubility coating, and a chemical stabilizer, provides high tungsten and titanium polish rates with high selectivity to silicon dioxide, and good oxide defectivity for use in tungsten local interconnect applications. A method for making a tungsten slurry includes first thoroughly blending small diameter alumina particles with a tight diameter range in an aqueous concentrate with a suspension agent, then mixing with water and oxidizers. Ferric salt tungsten slurries made by this method provide excellent tungsten polish characteristics for via plug and local interconnect applications.
摘要翻译： 抛光浆料组合物及其通过晶片的化学机械抛光来制造硅半导体晶片的平面化的方法。 使用三价铁钨氧化剂，过硫酸铵钛氧化剂，脂肪酸悬浮剂，小直径和紧密直径范围的氧化铝颗粒，涂覆有溶解度涂层和化学稳定剂的浆料配方提供高钨和钛抛光 对二氧化硅具有高选择性的速率，以及用于钨局部互连应用的良好的氧化物缺陷率。 一种制备钨浆料的方法包括首先用具有悬浮剂的含水浓缩物中将紧密直径范围的小直径氧化铝颗粒充分混合，然后与水和氧化剂混合。 通过该方法制备的铁盐钨浆通过插塞和局部互连应用提供优异的钨酸盐抛光特性。
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58.发明授权Method for determining metal work function by formation of Schottky diodes with shadow mask 有权通过用荫罩形成肖特基二极管来确定金属功函数的方法公开(公告)号：US07045384B1
公开(公告)日：2006-05-16
申请号：US10614031
申请日：2003-07-08
申请人： James N. Pan , Christy Mei-Chu Woo
发明人： James N. Pan , Christy Mei-Chu Woo
IPC分类号： H01L21/00
CPC分类号： H01L29/66143 , G01R31/2831
摘要： A method of determining a work function of a metal to be used as a metal gate material provides a metal-on-silicon (MS) Schottky diode on a silicon substrate. The MS Schottky diode is formed by deposition of the metal in a single step deposition through a shadow mask that is secured on the silicon substrate.
摘要翻译： 确定用作金属栅极材料的金属的功函数的方法在硅衬底上提供硅上金属（MS）肖特基二极管。 MS肖特基二极管通过在单个步骤沉积中沉积金属形成，该阴影掩模固定在硅衬底上。
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59.发明授权公开(公告)号：US06979625B1
公开(公告)日：2005-12-27
申请号：US10704595
申请日：2003-11-12
IPC分类号： H01L21/3213 , H01L21/331 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/32134 , H01L21/7684 , H01L21/76849 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the relatively wider openings. The filled openings are recessed and a metal capping layer deposited followed by CMP. The metal capping layer prevents diffusion along the copper-capping layer interface while the copper alloy filling the relatively wider openings impedes electromigration along the grain boundaries.
摘要翻译： 通过铜或低电阻铜合金形成高可靠的铜互连，填充较窄的开口并部分地填充相对较宽的开口，并且具有改进的电迁移电阻的铜合金选择性地沉积在较宽的开口中。 填充的开口凹陷并且金属覆盖层沉积，然后沉积CMP。 金属覆盖层防止沿着铜覆盖层界面的扩散，而填充相对较宽的开口的铜合金阻止沿着晶界的电迁移。
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60.发明授权Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP 失效屏蔽金属完整性测试采用双层线对线路泄漏测试模式和部分CMP公开(公告)号：US06531777B1
公开(公告)日：2003-03-11
申请号：US09599839
申请日：2000-06-22
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L22/14 , H01L22/34
摘要： A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing leakage or other electrical measurements between copper features on two different metal levels.
摘要翻译： 一种用于确定集成电路制造中多级铜金属化结构的阻挡层完整性的结构和方法。 新的测试结构防止铜CMP的任何导电残余物扩散到电介质层中。 通过在两个不同的金属层上的铜特征之间执行泄漏或其他电气测量来测试阻挡层的完整性。
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