公开(公告)号：US20080219082A1

公开(公告)日：2008-09-11

申请号：US12046150

申请日：2008-03-11

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C8/06 ,  G11C8/10

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

摘要翻译： 公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。 控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中 的非易失性存储单元。 此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。 此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

公开(公告)号：US07318896B2

公开(公告)日：2008-01-15

申请号：US10564448

申请日：2004-07-13

申请人： Kazuaki Shimamura ,  Toshihiro Tanaka

发明人： Kazuaki Shimamura ,  Toshihiro Tanaka

IPC分类号： C02F3/00

CPC分类号： C02F3/12 ,  C02F3/2846 ,  C02F3/286 ,  C02F2305/06 ,  Y02W10/15 ,  Y10S210/906

摘要： A method utilizing inorganic nutrient salts, which are inexpensive and easily usable, for waste water whose aerobic and/or anaerobic biological treatment cannot be established unless inorganic nutrient salts are added, is provided. A method and apparatus are provided for utilizing recovered magnesium ammonium phosphate, characterized by adding the recovered magnesium ammonium phosphate, which has been recovered from a treatment process for organic waste and/or organic waste water treatment, to a biological treatment step comprising an anaerobic treatment step and/or an aerobic treatment step to utilize the recovered magnesium ammonium phosphate as an inorganic nutrient source. Preferably, the recovered magnesium ammonium phosphate is utilized as particles, with its particle size being 0.5 mm or less, and/or the pH of a liquid, to which magnesium ammonium phosphate is added, being 10 or lower.

摘要翻译： 提供一种利用无机营养盐的方法，该方法是便宜且易于使用的，除非添加有机营养盐，否则无需建立需氧和/或厌氧生物处理的废水。 提供了一种用于利用回收的磷酸镁铵的方法和装置，其特征在于将从有机废物和/或有机废水处理的处理过程中回收的回收的磷酸镁铵添加到包括厌氧处理的生物处理步骤 步骤和/或需氧处理步骤，以利用回收的磷酸镁铵作为无机营养源。 优选地，将回收的磷酸镁铵用作颗粒，其粒度为0.5mm以下，和/或添加了磷酸镁铵的液体的pH为10以下。

公开(公告)号：US20070190528A1

公开(公告)日：2007-08-16

申请号：US10568695

申请日：2004-08-18

申请人： Toshihiro Tanaka ,  Yozo Ohnishi ,  Kouichi Ozaki ,  Aritoshi Iida ,  Masatsugu Hori ,  Yusuke Nakamura

发明人： Toshihiro Tanaka ,  Yozo Ohnishi ,  Kouichi Ozaki ,  Aritoshi Iida ,  Masatsugu Hori ,  Yusuke Nakamura

IPC分类号： C12Q1/68 ,  C07H21/04

CPC分类号： C12Q1/6883 ,  C12Q2600/136 ,  C12Q2600/156 ,  C12Q2600/158

摘要： An object of the present invention is to identify a novel single nucleotide polymorphism (SNP) associated with the onset and development of inflammatory diseases such as myocardial infarction. The present invention provides a method for judging inflammatory diseases which comprises detecting at least one gene polymorphism in the galectin-2 gene.

摘要翻译： 本发明的目的是鉴定与炎症性疾病如心肌梗塞的发病和发展相关的新型单核苷酸多态性（SNP）。 本发明提供一种判断炎性疾病的方法，其包括检测半乳凝素-2基因中的至少一种基因多态性。

公开(公告)号：US20070175822A1

公开(公告)日：2007-08-02

申请号：US10564483

申请日：2004-07-15

申请人： Kazumasa Kamachi ,  Yasuhiro Honma ,  Toshihiro Tanaka ,  Yuji Tsukamoto

发明人： Kazumasa Kamachi ,  Yasuhiro Honma ,  Toshihiro Tanaka ,  Yuji Tsukamoto

IPC分类号： C02F3/28

CPC分类号： C02F3/2846 ,  C02F2101/101 ,  C02F2209/265 ,  C12M21/04 ,  C12M41/34 ,  C12M47/18 ,  Y02E50/343 ,  Y10S210/916

摘要： An object of the present invention is to provide a process for a high-performance upflow anaerobic sludge treatment (methane fermentation treatment) targeting an organic wastewater containing an inorganic sulfur compound and an apparatus therefor. The invention relates to a process for methane fermentation treatment of an organic wastewater containing a sulfur compound, which includes: detecting a concentration of hydrogen sulfide in a biogas generated from a step of methane fermentation treatment; and, conducting a control of subjecting the organic wastewater to a desulfurization treatment operation in the case that the concentration of hydrogen sulfide in the biogas exceeds a predetermined value, and to an apparatus therefor. It is preferred that the predetermined value of the concentration of hydrogen sulfide is from 1% to 4%, preferably from 1% to 2%, and the desulfurization treatment operation comprises adding a desulfurizing agent containing an iron ion so that a molar ratio of the iron ion to sulfur is from 0.05 to 1.

摘要翻译： 本发明的目的是提供一种针对含有无机硫化合物的有机废水的高性能上流式厌氧污泥处理（甲烷发酵处理）及其装置的方法。 本发明涉及含有硫化合物的有机废水的甲烷发酵处理方法，其包括：检测由甲烷发酵处理步骤产生的沼气中的硫化氢浓度; 在生物气体中的硫化氢浓度超过规定值的情况下，对有机废水进行脱硫处理的控制，以及其设备的控制。 优选硫化氢浓度的预定值为1％至4％，优选1％至2％，脱硫处理操作包括加入含有铁离子的脱硫剂，使得 铁离子与硫离子为0.05〜1。

公开(公告)号：US07245531B2

公开(公告)日：2007-07-17

申请号：US11198191

申请日：2005-08-08

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。

公开(公告)号：US20060239072A1

公开(公告)日：2006-10-26

申请号：US11472993

申请日：2006-06-23

申请人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

发明人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.

摘要翻译： 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

公开(公告)号：US07072218B2

公开(公告)日：2006-07-04

申请号：US10486638

申请日：2002-07-03

申请人： Masamichi Fujito ,  Yuko Nakamura ,  Kazufumi Suzukawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa

发明人： Masamichi Fujito ,  Yuko Nakamura ,  Kazufumi Suzukawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC分类号： G11C16/04

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  G11C16/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high voltage output driver derives operational power from high voltages and a switching circuit which reverses the output state of the high voltage output driver. The high voltage output driver has in a current path of the high voltages, a series circuit of a first MOS transistor (M1) and second MOS transistor (M2), with the serial connection node thereof being the driver output terminal. The switching circuit operates to reverse the complementary switching states of the first and second MOS transistors such that one transistor in the on-state is switched to an off-state first and the other transistor is switched to an on-state afterward. Even if the other MOS transistor has its Vds exceeding the minimum breakdown voltage when it operates to turn on, the through current path is already shut off, and therefore the high voltage output driver does not break down.

摘要翻译： 高电压输出驱动器从高电压导出工作电源，并切换反向高压输出驱动器的输出状态的开关电路。 高压输出驱动器具有高电压的电流路径，第一MOS晶体管（M 1）和第二MOS晶体管（M 2）的串联电路，其串联连接节点是驱动器输出端子。 开关电路操作以反转第一和第二MOS晶体管的互补开关状态，使得处于导通状态的一个晶体管首先被切换到截止状态，而另一个晶体管之后被切换到导通状态。 即使其他MOS晶体管的Vds在其操作导通时其Vds超过最小击穿电压，直通电流路径已被切断，因此高压输出驱动器不会分解。

公开(公告)号：US20060123299A1

公开(公告)日：2006-06-08

申请号：US11329229

申请日：2006-01-11

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/021 ,  G01R31/30 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/3187 ,  G06F11/24 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/5004

摘要： A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

公开(公告)号：US20060028868A1

公开(公告)日：2006-02-09

申请号：US11198191

申请日：2005-08-08

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34 ,  G11C5/06

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。

公开(公告)号：US20050285181A1

公开(公告)日：2005-12-29

申请号：US11147243

申请日：2005-06-08

申请人： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

发明人： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3418 ,  G11C16/0466 ,  G11C16/3427 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/792

摘要： In a non-volatile semiconductor memory device using a charge storage film, it is intended to prevent a sequence disturb such as an erroneous write or erase of another memory cell on one and same word line which occurs depending on a bias transition path in stand-by state and write state. In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.

摘要翻译： 在使用电荷存储膜的非易失性半导体存储器件中，旨在防止在根据独立的偏置过渡路径发生的同一字线上的另一个存储单元的错误写入或擦除的序列干扰， 按状态和写状态。 关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为 存储晶体管被改变。 或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。