公开(公告)号：US20170148922A1

公开(公告)日：2017-05-25

申请号：US15181327

申请日：2016-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic ,  Joon Goo Hong ,  Rwik Sengupta

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78645

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.

公开(公告)号：US20170133513A1

公开(公告)日：2017-05-11

申请号：US15195886

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna Obradovic ,  Mark Rodder

IPC: H01L29/786 ,  H01L21/225 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78642 ,  H01L21/2256 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.

公开(公告)号：US20170110568A1

公开(公告)日：2017-04-20

申请号：US15169621

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dharmendar Reddy Palle ,  Borna Obradovic ,  Joon Goo Hong ,  Mark Rodder

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.

公开(公告)号：US20130149835A1

公开(公告)日：2013-06-13

申请号：US13690456

申请日：2012-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangsoo Son ,  Hyerim Moon ,  Hagju Cho ,  Jeongnam Han ,  Joon Goo Hong

IPC: H01L29/40

CPC classification number: H01L27/1104 ,  H01L21/823462 ,  H01L27/0207 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/517 ,  H01L29/7848

Abstract: A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners.

公开(公告)号：US11727258B2

公开(公告)日：2023-08-15

申请号：US17939807

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: G06N3/063 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78391

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US20230004789A1

公开(公告)日：2023-01-05

申请号：US17939807

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US11233008B2

公开(公告)日：2022-01-25

申请号：US16562291

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Kang-ill Seo ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L23/532

Abstract: A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.

公开(公告)号：US11217392B2

公开(公告)日：2022-01-04

申请号：US16417346

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Palle

IPC: H01L41/083 ,  H01G4/12 ,  H01L29/51 ,  H01L29/78 ,  H01G4/008

Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

公开(公告)号：US11101320B2

公开(公告)日：2021-08-24

申请号：US16850691

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G11C11/15 ,  H01L27/22 ,  G11C11/16 ,  G11C13/00 ,  H01F10/32 ,  H01L43/02 ,  H01L27/24

Abstract: A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

公开(公告)号：US20210118950A1

公开(公告)日：2021-04-22

申请号：US16850691

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: H01L27/22 ,  H01L27/24 ,  G11C11/16 ,  H01L43/02 ,  G11C13/00 ,  H01F10/32

Abstract: A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.