公开(公告)号：US10665299B1

公开(公告)日：2020-05-26

申请号：US16385430

申请日：2019-04-16

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Hong-Yan Chen

IPC: G11C16/04 ,  G11C16/00 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556 ,  G11C11/56

Abstract: Techniques are disclosed for reducing an injection type of read disturb in a memory device. During a program loop, when NAND strings in a selected sub-block are programmed, a pre-verify voltage pulse is applied to a selected word line and to a select gate transistor to discharge the drain-side channel in NAND strings of unselected sub-blocks. The duration of the pulse can vary for the different unselected sub-blocks and can be based on a sub-block programming order. In another aspect, the duration is higher for initial program loops in a program operation, when lower data states are being verified, and then decreases to a lower level for subsequent program loops when higher data states are being verified.

公开(公告)号：US10510413B1

公开(公告)日：2019-12-17

申请号：US16057423

申请日：2018-08-07

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Ching-Huang Lu

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  G11C16/08 ,  G11C16/28 ,  G11C16/16

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In a first program pass of a multi-pass program operation, pass voltages of the word lines adjacent to a selected word line are adjusted to increase electron injection in a portion of a charge-trapping layer between the selected word line and an adjacent source side unselected word line. In a second, final program pass of the multi-pass program operation, the pass voltages are adjusted to reduce electron injection in the portion of the charge-trapping layer between the selected word line and the adjacent source side unselected word line.

公开(公告)号：US10235294B1

公开(公告)日：2019-03-19

申请号：US15959445

申请日：2018-04-23

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Swaroop Kaza ,  Piyush Sagdeo

IPC: G11C11/34 ,  G06F12/0866 ,  G11C16/34 ,  G06F12/02

Abstract: Apparatuses and techniques are described for performing a pre-read operation in preparation for a read operation in a memory device. The pre-read operation transitions the memory cells from a first read condition to a second read condition so that their threshold voltages will be in a desired, predictable range when the read occurs. The pre-read operation can involve maintaining voltages on a selected word line and unselected word lines at specified levels and for a specified duration which is relatively long compared to a duration of the read operation. The word line voltages, in combination with bit line and source line voltages, provide the channels of a NAND string in a conductive state and gradually transitions the memory cells to the second read condition.

公开(公告)号：US10121552B1

公开(公告)日：2018-11-06

申请号：US15495178

申请日：2017-04-24

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yingda Dong ,  Ching-Huang Lu ,  Nan Lu ,  Hong-Yan Chen

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/32 ,  G11C16/08

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

公开(公告)号：US10008271B1

公开(公告)日：2018-06-26

申请号：US15693982

申请日：2017-09-01

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/30 ,  G11C16/08 ,  G11C7/14

CPC classification number: G11C16/10 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2213/75

Abstract: A memory device and associated techniques for reducing charge loss in a select gate transistor. A dummy memory cell is weakly programmed using a hot electron injection type of disturb to reduce the movement of holes toward the adjacent select gate transistor in a common charge trapping layer. The weak programming can occur in a program loop, e.g., in a transition between a pre-charge phase and a program phase, or in an erase loop, just after the erase of dummy and data memory cells. The weak programming does not involve a time penalty since it is concurrent with other operations. The disturb can be provided by increasing the control gate voltage of the dummy memory cell and/or decreasing the control gate voltage of the select gate transistor.

公开(公告)号：US20180166463A1

公开(公告)日：2018-06-14

申请号：US15893157

申请日：2018-02-09

Applicant: SanDisk Technologies LLC

Inventor： Hoon Cho ,  Jun Wan ,  Ching-Huang Lu

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/788 ,  H01L29/423 ,  H01L29/40 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/408 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/788 ,  H01L29/792

Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.

公开(公告)号：US09899410B1

公开(公告)日：2018-02-20

申请号：US15376925

申请日：2016-12-13

Applicant: SanDisk Technologies LLC

Inventor： Hoon Cho ,  Jun Wan ,  Ching-Huang Lu

IPC: H01L29/792 ,  H01L31/119 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/40 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/408 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/788 ,  H01L29/792

Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.

公开(公告)号：US20180033798A1

公开(公告)日：2018-02-01

申请号：US15445409

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Ching-Huang Lu ,  Yao-Sheng Lee ,  Jian Chen

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/28 ,  H01L23/532 ,  H01L27/11565 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

公开(公告)号：US09748266B1

公开(公告)日：2017-08-29

申请号：US15215080

申请日：2016-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Yanli Zhang ,  Liang Pang ,  Ching-Huang Lu ,  Matthias Baenninger ,  Yingda Dong

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/28282 ,  H01L27/1157

Abstract: A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.