公开(公告)号：US20180069515A1

公开(公告)日：2018-03-08

申请号：US15685079

申请日：2017-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE

IPC: H03F3/45 ,  G09G5/00 ,  H03K19/0185 ,  G05F3/26 ,  H03K19/003 ,  G09G3/36

CPC classification number: H03F3/45484 ,  G05F3/262 ,  G09G3/20 ,  G09G3/36 ,  G09G5/006 ,  G09G2370/08 ,  H03F3/4508 ,  H03K19/0016 ,  H03K19/003 ,  H03K19/018507

Abstract: To reduce power consumption and perform high-speed switching in boosting a voltage to a desired voltage. A semiconductor device includes a first buffer circuit, a level-shift circuit, and a second buffer circuit. The first buffer circuit includes a tri-state buffer circuit. The tri-state buffer circuit has a function of making each of an output of an input signal and an output of an inverted input signal into a resting state in response to a standby signal. The level-shift circuit includes a current mirror circuit, a differential amplifier circuit, and a switch circuit. The differential amplifier circuit has a function of controlling a current flowing through the current mirror circuit using the input signal and the inverted input signal as differential signals. The switch circuit has a function of making a current flowing through the differential amplifier circuit into a resting state in response to the standby signal.

公开(公告)号：US20160173097A1

公开(公告)日：2016-06-16

申请号：US14967592

申请日：2015-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  G11C5/147 ,  G11C7/04 ,  G11C7/14 ,  G11C8/08 ,  G11C11/403 ,  G11C11/4085 ,  G11C11/412 ,  G11C11/418 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1156 ,  H03K3/356182 ,  H03K19/0016

Abstract: To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. When the semiconductor device returns to a normal state, the second potential is supplied, so that the potential of a node in the level shifter circuit increases. To utilize the increase in the second potential or suppress malfunction due to the increase in the potential, capacitors are provided in the level shifter circuit. This inhibits unexpected operation of a transistor in the level shifter circuit.

Abstract translation: 提供在电源电压上升之后立即抑制高电平信号的意外输出的半导体器件。 半导体器件包括第一缓冲电路，电平移位器电路和第二缓冲电路。 第一电位被提供给第一缓冲电路，第二电位被提供给电平移位器电路和第二缓冲电路; 因此，半导体器件返回到正常状态。 当半导体器件返回到正常状态时，提供第二电位，使得电平移位器电路中的节点的电位增加。 为了利用第二电位的增加或由于电位的增加而抑制故障，在电平移位电路中提供电容器。 这抑制了电平移位器电路中的晶体管的意外的操作。

公开(公告)号：US20160134789A1

公开(公告)日：2016-05-12

申请号：US14935721

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Yuki OKAMOTO

IPC: H04N5/225 ,  H01L27/146

CPC classification number: H04N5/2253 ,  H01L27/14612 ,  H01L27/14692 ,  H04N5/3696 ,  H04N5/37452 ,  H04N5/378

Abstract: To provide an imaging device capable of obtaining high-quality imaging data. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes an eighth transistor. The imaging device can compensate variation in threshold voltage of an amplifier transistor included in the first circuit.

Abstract translation: 提供能够获得高质量成像数据的成像装置。 成像装置包括第一电路和第二电路。 第一电路包括光电转换元件，第一晶体管，第二晶体管，第三晶体管，第四晶体管，第五晶体管，第六晶体管，第七晶体管，第一电容器，第二电容器和第三电容器。 第二电路包括第八晶体管。 成像装置可以补偿包括在第一电路中的放大器晶体管的阈值电压的变化。

公开(公告)号：US20160027784A1

公开(公告)日：2016-01-28

申请号：US14873278

申请日：2015-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Shuhei NAGATSUKA ,  Takanori MATSUZAKI ,  Hiroki INOUE

IPC: H01L27/108

CPC classification number: H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

公开(公告)号：US20150380450A1

公开(公告)日：2015-12-31

申请号：US14746926

申请日：2015-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA ,  Hiroki INOUE ,  Takuro OHMARU

IPC: H01L27/146 ,  H01L31/105 ,  H01L31/0272 ,  H01L29/786

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14641 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/0272 ,  H01L31/105

Abstract: An imaging device with high productivity and improved dynamic range is provided. The imaging device includes a pixel driver circuit and a photoelectric conversion element including a p-type semiconductor, an n-type semiconductor, and an i-type semiconductor. In a plan view, the total area of a part of the i-type semiconductor overlapped with neither a metal material nor a semiconductor material constituting the pixel driver circuit is preferably greater than or equal to 65%, more preferably greater than or equal to 80%, and still more preferably greater than or equal to 90% of the area of the whole i-type semiconductor. Plural photoelectric conversion elements are provided in the same semiconductor, whereby a process for separating the photoelectric conversion elements can be omitted. The i-type semiconductors in the plural photoelectric conversion elements are separated from each other by the p-type semiconductor or the n-type semiconductor.

Abstract translation: 提供了具有高生产率和改进的动态范围的成像装置。 该成像装置包括像素驱动电路和包括p型半导体，n型半导体和i型半导体的光电转换元件。 在平面图中，与构成像素驱动电路的金属材料和半导体材料不重叠的i型半导体的一部分的总面积优选为65％以上，更优选为80以上 ％，还更优选大于或等于整个i型半导体的面积的90％。 多个光电转换元件设置在相同的半导体中，由此可以省略用于分离光电转换元件的处理。 多个光电转换元件中的i型半导体通过p型半导体或n型半导体彼此分离。

公开(公告)号：US20150294693A1

公开(公告)日：2015-10-15

申请号：US14681570

申请日：2015-04-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI ,  Hiroki INOUE ,  Shuhei NAGATSUKA ,  Yuto YAKUBO

IPC: G11C5/02 ,  H01L27/12 ,  G11C5/06 ,  H01L29/24

CPC classification number: G11C5/025 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24

Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。

公开(公告)号：US20140027882A1

公开(公告)日：2014-01-30

申请号：US14037778

申请日：2013-09-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Hiroki INOUE

IPC: H01L49/02

CPC classification number: H01L21/02683 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/1296 ,  H01L28/40

Abstract: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.

Abstract translation: 在包括数字电路部分和具有设置在衬底上的电容器部分的模拟电路部分的半导体器件中，电容器部分设置有第一布线，第二布线和多个具有多个电容器元件的块。 此外，设置在每个块中的多个电容器元件中的每一个具有半导体膜，该半导体膜具有第一杂质区和设置有分隔开第一杂质区的多个第二杂质区，并且在第一杂质区上设置有导电膜， 绝缘膜。 由第一杂质区，绝缘膜和导电膜形成电容器。