公开(公告)号：US20160054362A1

公开(公告)日：2016-02-25

申请号：US14830817

申请日：2015-08-20

Applicant: Semiconductor Energy Laboratory Co., LTD.

Inventor： Masashi TSUBUKU ,  Shunpei YAMAZAKI ,  Hidetomo KOBAYASHI ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Toshihiko TAKEUCHI

IPC: G01R19/25 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/24 ,  G01R19/0092 ,  G01R31/2608 ,  G01R31/2621 ,  H01L22/14 ,  H01L27/0629 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A current measurement method with which an extremely low current can be measured is provided. In the method, a charge written to a first terminal of a capacitor through a transistor under test is retained, data on the correspondence between a potential V of the first terminal of the capacitor and Time t is generated, and a stretched exponential function represented by Formula (a1) is fitted to the data to determine parameters of Formula (a1). The derivative of Formula (a1) with respect to time gives a stretched exponential function describing an off-state current of the transistor under test. The potential of the first terminal of the capacitor is measured using an on-state current of a transistor whose gate is connected to the first terminal of the capacitor. V FN  ( t ) = α ×  - ( t τ ) β ( a   1 )

Abstract translation: 提供了可以测量极低电流的电流测量方法。 在该方法中，保持通过被测晶体管向电容器的第一端子写入的电荷，产生电容器的第一端子的电位V与时间t之间的对应关系的数据，以及由 公式（a1）拟合到数据中以确定公式（a1）的参数。 式（a1）相对于时间的导数给出描述被测晶体管截止电流的拉伸指数函数。 使用其栅极连接到电容器的第一端子的晶体管的导通状态电流来测量电容器的第一端子的电位。 V FN（t）=α× - （tτ）＆bgr; （一个1）

公开(公告)号：US20150364502A1

公开(公告)日：2015-12-17

申请号：US14834736

申请日：2015-08-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masayuki SAKAKURA ,  Yoshiaki OIKAWA ,  Kenichi OKAZAKI ,  Hotaka MARUYAMA ,  Masashi TSUBUKU

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/133528 ,  G02F1/1337 ,  G02F1/1339 ,  G02F1/13394 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136204 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/133357 ,  G02F2201/123 ,  G11C19/28 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/247 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.

公开(公告)号：US20150340509A1

公开(公告)日：2015-11-26

申请号：US14819772

申请日：2015-08-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

Abstract translation: 本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。 通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（ 使用第一材料膜作为核的结晶氧化物半导体膜）。 作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。

公开(公告)号：US20150294994A1

公开(公告)日：2015-10-15

申请号：US14688232

申请日：2015-04-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masahiro TAKAHASHI ,  Takuya HIROHASHI ,  Masashi TSUBUKU ,  Noritaka ISHIHARA ,  Masashi OOTA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  C23C14/086 ,  G01N23/207 ,  G02F1/1368 ,  H01L21/0237 ,  H01L21/02422 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L22/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nmφ and less than or equal to 10 nmφ.

Abstract translation: 提供了包括晶体部分并且具有高度稳定的物理性质的金属氧化物膜。 晶体部分的尺寸小于或等于10nm，这允许在测量面积大于或等于5nm＆phgr时观察金属氧化物膜横截面的纳米束电子衍射图中的周向排列的斑点 ; 小于等于10nm。

公开(公告)号：US20150236163A1

公开(公告)日：2015-08-20

申请号：US14628439

申请日：2015-02-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78696 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H02M3/073 ,  H02M3/158

Abstract: A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×1014/cm3 or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.

Abstract translation: 晶体管包括栅极，源极和漏极，栅极电连接到源极或漏极，第一信号被输入到源极和漏极中的一个，以及载流子浓度为5× 1014 / cm3以下用于沟道形成层。 电容器包括第一电极和第二电极，第一电极电连接到晶体管的源极和漏极中的另一个，并且作为时钟信号的第二信号被输入到第二电极。 第一信号的电压被升高或降低以获得通过晶体管的源极和漏极中的另一个输出作为输出信号的第三信号。

公开(公告)号：US20150048368A1

公开(公告)日：2015-02-19

申请号：US14527076

申请日：2014-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Ryosuke WATANABE ,  Masashi OOTA ,  Noritaka ISHIHARA ,  Koki INOUE

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L22/14 ,  H01L29/247 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

Abstract translation: 提供了不容易引起晶体管的电特性变化并且具有高稳定性的氧化物半导体层叠膜。 此外，提供了在其沟道形成区域中包括氧化物半导体层叠膜并且具有稳定的电特性的晶体管。 氧化物半导体层叠膜包括依次堆叠并且各自含有铟，镓和锌的第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层。 第二氧化物半导体层中的铟的含量百分比高于第一氧化物半导体层和第三氧化物半导体层中的铟的含量百分比，并且通过CPM测量的氧化物半导体层叠膜的吸收系数低于或等于 在1.5eV至2.3eV的能量范围内等于3×10-3 / cm。

公开(公告)号：US20140368417A1

公开(公告)日：2014-12-18

申请号：US14477172

申请日：2014-09-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Ryo ARASAWA ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: G09G3/36 ,  H01L27/12 ,  H01L29/786

CPC classification number: G09G3/3614 ,  G02F1/133553 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2201/123 ,  G02F2202/10 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/08 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  H01L21/02164 ,  H01L21/02266 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/467 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×1014/cm3.

Abstract translation: 在包括显示部分中的多个像素并且被配置为在多个帧周期中进行显示的液晶显示装置中，每个帧周期包括写入周期和保持周期，并且在将图像信号输入到每个 在所述写入周期中的所述多个像素中，包括在所述多个像素中的每一个中的晶体管被​​截止，并且所述图像信号在所述保持周期中保持至少30秒。 像素包括具有氧化物半导体层的半导体层，氧化物半导体层的载流子浓度小于1×10 14 / cm 3。

公开(公告)号：US20140357018A1

公开(公告)日：2014-12-04

申请号：US14459548

申请日：2014-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kengo AKIMOTO ,  Masashi TSUBUKU

IPC: H01L29/66 ,  H01L27/12

CPC classification number: H01L29/66742 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/324 ,  H01L21/447 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/7869

Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.

Abstract translation: 为了提供一种制造薄膜晶体管的方法，其中氧化物半导体层和源极和漏极电极层之间的接触电阻很小，源极和漏极电极层的表面用等离子体和含有氧化物半导体层的氧化物半导体层进行溅射处理 In，Ga和Zn依次形成在源极和漏极电极层上，而不会将源极和漏极电极层暴露于空气。

公开(公告)号：US20140231802A1

公开(公告)日：2014-08-21

申请号：US14264301

申请日：2014-04-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masayuki SAKAKURA ,  Yoshiaki OIKAWA ,  Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2202/10 ,  H01L27/1225 ,  H01L27/1255

Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.

Abstract translation: 半导体器件包括驱动器电路部分，其包括驱动器电路和包括像素的像素部分。 像素包括具有透光性的栅极电极层，栅极绝缘层，源极电极层和漏极电极层，其各自具有设置在栅极绝缘层上的透光性，覆盖顶表面的氧化物半导体层和 源极电极层和漏极电极层的侧面，并且在栅电极层之间设置有栅极绝缘层，导电层设置在氧化物半导体层的一部分上，并且具有比源极电极层和漏极 电极层和与氧化物半导体层的一部分接触的氧化物绝缘层。

公开(公告)号：US20140034946A1

公开(公告)日：2014-02-06

申请号：US13953428

申请日：2013-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Ryosuke WATANABE ,  Masashi OOTA ,  Noritaka ISHIHARA ,  Koki INOUE

IPC: H01L29/24 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L22/14 ,  H01L29/247 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

Abstract translation: 提供了不容易引起晶体管的电特性变化并且具有高稳定性的氧化物半导体层叠膜。 此外，提供了在其沟道形成区域中包括氧化物半导体层叠膜并且具有稳定的电特性的晶体管。 氧化物半导体层叠膜包括依次堆叠并且各自含有铟，镓和锌的第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层。 第二氧化物半导体层中的铟的含量百分比高于第一氧化物半导体层和第三氧化物半导体层中的铟的含量百分比，并且通过CPM测量的氧化物半导体层叠膜的吸收系数低于或等于 在1.5eV至2.3eV的能量范围内等于3×10-3 / cm。