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    Device of physically unclonable function with floating gate transistors, and manufacturing method
    51.
    发明授权
    Device of physically unclonable function with floating gate transistors, and manufacturing method 有权

    公开(公告)号：US11546177B2

    公开(公告)日：2023-01-03

    申请号：US16784495

    申请日：2020-02-07

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa

    IPC: H04L29/06 ,  H04L9/32 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  H04L9/06

    Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of floating gate transistor pairs, floating gate transistors of the set of floating gate transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of floating gate transistors of floating gate transistor pairs of the set of floating gate transistor pairs, and to identify a floating gate transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable floating gate transistor pair; and a write circuit configured to shift the effective threshold voltage of a floating gate transistor of the unreliable floating gate transistor pair to be inside the common random distribution.

    Power-on-reset circuit and corresponding electronic device
    52.
    发明授权
    Power-on-reset circuit and corresponding electronic device 有权

    公开(公告)号：US11171644B2

    公开(公告)日：2021-11-09

    申请号：US17207382

    申请日：2021-03-19

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

    Inventor： Antonino Conte ,  Francesco Tomaiuolo ,  Francesco La Rosa

    IPC: H03K17/14 ,  H03K17/22

    Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

    COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING IN A DIELECTRIC INTERFACE
    55.
    发明申请
    COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING IN A DIELECTRIC INTERFACE 审中-公开

    公开(公告)号：US20190371805A1

    公开(公告)日：2019-12-05

    申请号：US16542511

    申请日：2019-08-16

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L27/11563 ,  H01L27/11536

    Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.

    RING OSCILLATOR OPERATION MANAGEMENT METHOD AND APPARATUS
    60.
    发明申请
    RING OSCILLATOR OPERATION MANAGEMENT METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20180091094A1

    公开(公告)日：2018-03-29

    申请号：US15436817

    申请日：2017-02-19

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa

    IPC: H03B1/02 ,  H03K3/03 ,  G11C7/06

    CPC classification number: H03K3/0315 ,  G05F3/262 ,  G11C7/062 ,  H03K3/011 ,  H03L1/00 ,  H03L5/00 ,  H03L7/0995

    Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.

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