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51.发明授权公开(公告)号：US07301107B2
公开(公告)日：2007-11-27
申请号：US10694611
申请日：2003-10-27
IPC分类号： H05K1/11
CPC分类号： H01L23/5222 , H01L21/565 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/49575 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.
摘要翻译： 设计用于降低层间和层间电容的半导体器件的互连结构，并且包括下金属层和上金属层以及介于金属层之间的绝缘层。 下金属层和上金属层中的每一个包括间隔开并在低k电介质材料内延伸的多条导线。 多个金属填充的通孔将下金属层的导线与上金属层的导电线互连。 绝缘层还包括设置在相邻的金属填充通孔之间的低k电介质材料。 已经在上下金属层的导电线之间的低k电介质材料中蚀刻的开口和金属填充的通孔，在开口内沉积超低k材料。 超低k和低d介电材料的集成降低了结构的总体电容以增强性能。
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公开(公告)号：US07068139B2
公开(公告)日：2006-06-27
申请号：US10953475
申请日：2004-09-29
IPC分类号： H01F5/00
CPC分类号： H01L24/10 , H01F41/041 , H01L23/5227 , H01L24/13 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2224/48
摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
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53.发明授权公开(公告)号：US06730600B2
公开(公告)日：2004-05-04
申请号：US10259256
申请日：2002-09-27
IPC分类号： H01L21465
CPC分类号： H01L21/32135 , C23F1/12
摘要： A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.
摘要翻译： 通过使材料与蚀刻剂气体化学反应来进行用于干蚀刻沉积在半导体器件上的材料的方法。 蚀刻工艺在反应室内以预定温度和预定压力在反应室内进行，而不需要在室内产生等离子体或向半导体器件施加电偏压。 将足够量的气体引入反应室以选择性地从半导体器件中去除材料。
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公开(公告)号：US06720261B1
公开(公告)日：2004-04-13
申请号：US09586586
申请日：2000-06-02
申请人： Steven Mark Anderson , Siddhartha Bhowmik , Joseph William Buckfeller , Sailesh Mansinh Merchant , Frank Minardi
发明人： Steven Mark Anderson , Siddhartha Bhowmik , Joseph William Buckfeller , Sailesh Mansinh Merchant , Frank Minardi
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , Y02P80/30
摘要： A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.
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55.发明授权Chemical mechanical polishing composition and method of polishing metal layers using same 有权化学机械抛光组合物及使用其研磨金属层的方法公开(公告)号：US06599837B1
公开(公告)日：2003-07-29
申请号：US09515730
申请日：2000-02-29
IPC分类号： H01L21302
CPC分类号： C09K3/1463 , C09G1/02 , H01L21/3212
摘要： The present invention provides a chemical mechanical planarization (CMP) polishing composition that polishes metal layers at a good removal rate and that provides good planarization of metal layers in a process that can be readily controlled. The CMP polishing composition of the present composition includes a plurality of abrasive particles, a triazole or a triazole derivative, a ferricyanide salt oxidizing agent and water and has a pH of from about 1 to about 6. In addition, the present invention includes a method for removing at least a portion of a metallization layer by polishing a metallization layer using the CMP polishing composition of the invention.
摘要翻译： 本发明提供了一种化学机械平面化（CMP）抛光组合物，其以良好的去除速率抛光金属层并且在易于控制的工艺中提供良好的金属层平面化。 本发明组合物的CMP抛光组合物包括多个研磨颗粒，三唑或三唑衍生物，铁氰化物盐氧化剂和水，并且其pH为约1至约6.另外，本发明包括一种方法 用于通过使用本发明的CMP抛光组合物抛光金属化层来去除至少一部分金属化层。
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56.发明授权Method of making a graded grown, high quality oxide layer for a semiconductor device 有权制造用于半导体器件的分级生长的高质量氧化物层的方法公开(公告)号：US06541394B1
公开(公告)日：2003-04-01
申请号：US09481992
申请日：2000-01-11
IPC分类号： H01L2131
CPC分类号： H01L21/28202 , C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/02304 , H01L21/02312 , H01L21/28185 , H01L21/28211 , H01L21/28273 , H01L21/31604 , H01L21/31612 , H01L21/31662 , H01L21/3185 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for making an oxide layer on a silicon substrate produces an oxide layer including graded portions with greatly reduced stress. The method includes growing a first oxide portion over a substrate by upwardly ramping the substrate to a first temperature lower than a SiO2 viscoelastic temperature. Thereafter a second oxide portion is grown between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the SiO2 viscoelastic temperature. The second oxide portion may have a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.
摘要翻译： 在硅衬底上制造氧化物层的方法产生包括具有大大降低的应力的渐变部分的氧化物层。 该方法包括通过将衬底向上倾斜到低于SiO 2粘弹性温度的第一温度而在衬底上生长第一氧化物部分。 此后，在高于SiO 2粘弹性温度的第二温度下，通过将硅衬底暴露于氧化环境，在第一氧化物部分和硅衬底之间生长第二氧化物部分。 第二氧化物部分可以具有梯度氧化物层的总厚度的约25至50％范围内的厚度。
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公开(公告)号：US06471925B1
公开(公告)日：2002-10-29
申请号：US09488899
申请日：2000-01-21
IPC分类号： B01D5362
CPC分类号： C23C16/4412 , B01D53/864 , B01D53/8675
摘要： A method for treating an effluent gas from a semiconductor processing system includes the steps of exhausting the effluent gas from a processing chamber, and catalytically treating the effluent gas with the at least one mixed metal oxide. The effluent gas includes unconsumed process gasses introduced during semiconductor processing operations, such as during chemical vapor deposition (CVD) and plasma-reactive ion etching. The mixed metal oxide may include a hetero bi-metal oxide, a hetero tri-metal oxide, or a perovskite. A hetero bi-metal oxide includes LaCoO3 and LaMnO3, for example, and a hetero tri-metal oxide includes (LaxPr1−x)CoO3 and (LaxPr1−x)MnO3, for example. The effluent gas may include at least carbon monoxide and/or ozone. Thus, catalytically treating the effluent gas preferably includes the catalytically converting carbon monoxide to carbon dioxide and/or ozone to oxygen. With the effluent gas being treated by the catalytic converter prior to being released into the atmosphere, undesirable gases, such as carbon monoxide and unreacted ozone are efficiently converted into non-harmful carbon dioxide and oxygen.
摘要翻译： 用于处理来自半导体处理系统的流出气体的方法包括以下步骤：从处理室排出废气，并用至少一种混合金属氧化物催化处理流出气体。 废气包括在半导体加工操作期间引入的未消耗的工艺气体，例如在化学气相沉积（CVD）和等离子体反应离子蚀刻期间。 混合金属氧化物可以包括异双金属氧化物，杂三金属氧化物或钙钛矿。 例如，异双金属氧化物包括LaCoO 3和LaMnO 3，并且异三金属氧化物包括（LaxPr1-x）CoO3和（LaxPr1-x）MnO3。 废气可以至少包括一氧化碳和/或臭氧。 因此，催化处理废气优选包括将一氧化碳催化转化为二氧化碳和/或臭氧至氧气。 废气在被排放到大气中之前被催化转化器处理，有害的气体如一氧化碳和未反应的臭氧被有效地转化成无害的二氧化碳和氧气。
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公开(公告)号：US06436830B1
公开(公告)日：2002-08-20
申请号：US09413741
申请日：1999-10-06
IPC分类号： H01L21302
CPC分类号： B24B37/042 , B24B57/02
摘要： A chemical mechanical polishing (CMP) system includes a polishing device including a polishing article. The polishing device holds the semiconductor wafer and provides relative movement between the semiconductor wafer and the polishing article with a slurry therebetween. The CMP system also includes a slurry processor for processing used slurry from the polishing device and for delivering processed slurry to the polishing device. The slurry processor including a metal separator for separating metal particles, polished from the semiconductor wafer, from the used slurry. The slurry can be continuously recirculated during a CMP process without damaging and/or contaminating the layers of the semiconductor wafer.
摘要翻译： 化学机械抛光（CMP）系统包括包括抛光制品的抛光装置。 抛光装置保持半导体晶片，并且在半导体晶片和抛光制品之间具有浆料之间的相对移动。 CMP系统还包括用于处理来自抛光装置的所用浆料并将处理过的浆料输送到抛光装置的浆料处理器。 浆料处理器包括用于从所用浆料中分离从半导体晶片抛光的金属颗粒的金属分离器。 浆料可以在CMP工艺期间连续再循环，而不损坏和/或污染半导体晶片的层。
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公开(公告)号：US06410986B1
公开(公告)日：2002-06-25
申请号：US09218574
申请日：1998-12-22
IPC分类号： H01L2352
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A titanium nitride barrier within an integrated contact structure is formed as multi-layered stack. The multi-layering of the titanium nitride thus provides improved junction integrity since the multi-layer structure exhibits improved mechanical stability when compared to conventional single layer arrangements. The multi-layer titanium nitride barrier may be used as either a conventional interconnect metallization or as a nucleation structure within a tungsten plug. The multi-layer structure may be formed to include an overall thickness less than a conventional single layer, yet provide for improved stress accommodation, resulting in eliminating micro-cracks within the titanium nitride (and as a result eliminating the un-wanted diffusion of aluminum or tungsten precursors through the titanium nitride).
摘要翻译： 集成接触结构内的氮化钛屏障形成为多层叠层。 因此，与常规单层布置相比，多层结构表现出改善的机械稳定性，因此氮化钛的多层化提供了改进的接合完整性。 多层氮化钛屏障可以用作钨插塞中的常规互连金属化或成核结构。 多层结构可以形成为包括小于常规单层的总厚度，但是提供改进的应力调节，导致消除氮化钛内的微裂纹（并且因此消除了铝的不希望的扩散 或钨前体通过氮化钛）。
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60.发明授权公开(公告)号：US06410419B1
公开(公告)日：2002-06-25
申请号：US09633241
申请日：2000-08-07
IPC分类号： H01L214763
CPC分类号： H01L21/76831
摘要： Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.
摘要翻译： 多孔电介质材料中的互连件涂覆有含SiC材料，以抑制电介质材料内的水分渗透和保留。 具体地，掺杂有诸如SiC（BN）的硼的SiC涂层显示出作为电介质互连的阻挡层的特别好的结果。
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