公开(公告)号：US20160284858A1

公开(公告)日：2016-09-29

申请号：US15081129

申请日：2016-03-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Yoko TSUKAMOTO

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/42392 ,  H01L29/78696

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

Abstract translation: 提供具有高度稳定的电气特性的小型化晶体管。 此外，在包括晶体管的半导体器件中，也实现了高性能和高可靠性。 晶体管包括在衬底上的导体，氧化物半导体和绝缘体。 氧化物半导体包括第一区域和第二区域。 第二区域的电阻低于第一区域的电阻。 氧化物半导体中的第一区域的整个表面通过绝缘体插入其间的导体被所有方向包围。

公开(公告)号：US20150053975A1

公开(公告)日：2015-02-26

申请号：US14501965

申请日：2014-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA ,  Mizuho SATO ,  Mitsuhiro ICHIJO ,  Toshiya ENDO

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

Abstract translation: 在具有栅极结构的晶体管中，栅电极层与其间插入有栅极绝缘层的沟道区域的氧化物半导体层重叠，当绝缘层中含有大量的氢时，氢扩散 由于绝缘层与氧化物半导体层接触，所以进入氧化物半导体层; 因此，晶体管的电特性降低。 本发明的目的是提供一种具有良好电特性的半导体器件。 与形成沟道区域的氧化物半导体层接触的绝缘层使用其氢浓度小于6×1020原子/ cm3的绝缘层。 使用绝缘层，可以防止氢的扩散，并且可以提供具有良好电特性的半导体器件。

公开(公告)号：US20140011319A1

公开(公告)日：2014-01-09

申请号：US14013383

申请日：2013-08-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA ,  Mizuho SATO

IPC: H01L29/66

CPC classification number: H01L21/02554 ,  H01L21/02488 ,  H01L21/02664 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract translation: 使用含有硅氧化物自由基的绝缘层作为与用于形成沟道的氧化物半导体层接触的绝缘层。 氧从绝缘层释放，由此可以减少氧化物半导体层中的氧缺乏和绝缘层与氧化物半导体层之间的界面状态。 因此，可以制造可靠性高，电特性变化小的半导体装置。

公开(公告)号：US20130175530A1

公开(公告)日：2013-07-11

申请号：US13733536

申请日：2013-01-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei NODA ,  Yuta ENDO

IPC: H01L29/786

CPC classification number: H01L29/78693 ,  H01L27/1255 ,  H01L29/04 ,  H01L29/785 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a fin-type transistor having an oxide semiconductor in a channel formation region in which the channel formation region comprising an oxide semiconductor is three-dimensionally structured and a gate electrode is arranged to extend over the channel formation region. Specifically, the fin-type transistor comprises: an insulator protruding from a substrate plane; an oxide semiconductor film extending beyond the insulator; a gate insulating film over the oxide semiconductor film; and a gate electrode over and extending beyond the oxide semiconductor film. This structure allows the expansion of the width of the channel formation region, which enables the miniaturization and high integration of a semiconductor device having the transistor. Additionally, the extremely small off-state current of the transistor contributes to the formation of a semiconductor device with significantly reduced power consumption.

Abstract translation: 提供了在通道形成区域中具有氧化物半导体的翅片型晶体管，其中包括氧化物半导体的沟道形成区域是三维构造的，并且栅电极被布置成在沟道形成区域上延伸。 具体地，鳍型晶体管包括：从基板平面突出的绝缘体; 延伸超过绝缘体的氧化物半导体膜; 氧化物半导体膜上的栅极绝缘膜; 以及在氧化物半导体膜之上并延伸超过氧化物半导体膜的栅电极。 这种结构允许扩大通道形成区域的宽度，这使得能够使具有晶体管的半导体器件的小型化和高集成化。 此外，晶体管的非常小的截止状态电流有助于形成具有显着降低的功耗的半导体器件。

公开(公告)号：US20250008748A1

公开(公告)日：2025-01-02

申请号：US18885848

申请日：2024-09-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/408 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20240315038A1

公开(公告)日：2024-09-19

申请号：US18613222

申请日：2024-03-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tomoaki ATSUMI ,  Yuta ENDO

IPC: H10B43/35 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  G11C16/0466 ,  G11C16/0483 ,  H10B43/27 ,  H10B43/40 ,  G11C16/10 ,  G11C16/26

Abstract: A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

公开(公告)号：US20220037323A1

公开(公告)日：2022-02-03

申请号：US17503651

申请日：2021-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takayuki IKEDA ,  Kiyoshi KATO ,  Yuta ENDO ,  Junpei SUGAO

IPC: H01L27/108 ,  G11C5/02 ,  G11C11/403 ,  G11C11/409 ,  H01L29/24

Abstract: A semiconductor device with a large storage capacity per unit area is provided.
A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

公开(公告)号：US20210398988A1

公开(公告)日：2021-12-23

申请号：US17466442

申请日：2021-09-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/786 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-lth sub memory cell.

公开(公告)号：US20210384353A1

公开(公告)日：2021-12-09

申请号：US16637384

申请日：2018-08-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuta ENDO ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/12

Abstract: A semiconductor device that can be highly integrated is provided.
The semiconductor device includes first and second transistors and first and second capacitors. Each of the first and second transistors includes a gate insulator and a gate electrode over an oxide. Each of the first and second capacitors includes a conductor, a dielectric over the conductor, and the oxide. The first and second transistors are provided between the first capacitor and the second capacitor. One of a source and a drain of the first transistor is also used as one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is also used as one electrode of the first capacitor. The other of the source and the drain of the second transistor is also used as one electrode of the second capacitor. The channel lengths of the first and second transistors are larger than the lengths in a direction parallel to short sides of fourth and fifth conductors.

公开(公告)号：US20200266281A1

公开(公告)日：2020-08-20

申请号：US16755208

申请日：2018-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tomoki HIRAMATSU ,  Yusuke NONAKA ,  Noritaka ISHIHARA ,  Shota SAMBONSUGE ,  Yasumasa YAMANE ,  Yuta ENDO

IPC: H01L29/51 ,  H01L21/8238

Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first insulator; a first oxide provided over the first insulator; a second oxide provided over the first oxide; a first conductor and a second conductor provided apart from each other over the second oxide; a third oxide provided over the second oxide, the first conductor, and the second conductor; a second insulating film provided over the third oxide; and a third conductor provided over the second oxide with the third oxide and the second insulating film positioned therebetween. The third oxide contains a metal element and nitrogen, and the metal element is bonded to nitrogen.