公开(公告)号：US20120085495A1

公开(公告)日：2012-04-12

申请号：US13326940

申请日：2011-12-15

申请人： Hyo-San Lee ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Jeong-Nam Han ,  Jung-Min Oh ,  Kwon-Tack Lim ,  Ha-Soo Hwang ,  Haldori Vuvaraj ,  Jae-Monk Jung

发明人： Hyo-San Lee ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Jeong-Nam Han ,  Jung-Min Oh ,  Kwon-Tack Lim ,  Ha-Soo Hwang ,  Haldori Vuvaraj ,  Jae-Monk Jung

IPC分类号： C23F1/08 ,  B08B3/00

CPC分类号： H01L21/02101 ,  H01L21/31111 ,  H01L21/67051 ,  H01L21/6708 ,  H01L27/10852 ,  Y10S134/902

摘要： Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.

公开(公告)号：US08124526B2

公开(公告)日：2012-02-28

申请号：US12503440

申请日：2009-07-15

申请人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

发明人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

IPC分类号： H01L21/4763

CPC分类号： H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

摘要翻译： 在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。 使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。 浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

公开(公告)号：US08034705B2

公开(公告)日：2011-10-11

申请号：US12460318

申请日：2009-07-16

申请人： Suk-Hun Choi ,  Chang-Ki Hong ,  Yoon-Ho Son ,  Ju-Young Jung

发明人： Suk-Hun Choi ,  Chang-Ki Hong ,  Yoon-Ho Son ,  Ju-Young Jung

IPC分类号： H01L21/4763

CPC分类号： H01L21/76888 ,  H01L21/76879 ,  H01L21/76883 ,  H01L27/24

摘要： A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.

摘要翻译： 插头包括第一绝缘中间层，钨图案和氧化钨图案。 第一绝缘中间层具有在基板上形成的接触孔。 钨图案形成在接触孔中。 钨图案具有比第一绝缘中间层的上表面低的顶表面。 氧化钨图案形成在接触孔和钨图案上。 氧化钨图案具有水平面。

公开(公告)号：US20100187654A1

公开(公告)日：2010-07-29

申请号：US12659724

申请日：2010-03-18

申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

IPC分类号： H01L29/92

CPC分类号： H01L28/91 ,  H01L21/31116 ,  H01L27/10817 ,  H01L27/10852

摘要： A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

摘要翻译： 可以提供具有电容器的半导体器件及其制造方法。 制造半导体器件的方法可以包括在衬底上顺序地形成蚀刻停止层和模制层，图案化模具层以形成露出蚀刻停止层的一部分的模具电极孔，通过以下步骤选择性地蚀刻暴露的蚀刻停止层： 各向同性干蚀刻工艺，以形成通过蚀刻停止层的接触电极孔，以露出衬底的一部分，在衬底上形成导电层，并去除模层上的模层上的导电层，形成圆柱形底电极 在模具和接触电极孔中。 各向同性干蚀刻工艺可以利用包括主蚀刻气体和选择性调节气体的工艺气体。 选择性调节气体可以通过各向同性湿蚀刻工艺增加蚀刻停止层的蚀刻速率超过模具层的蚀刻速率。

公开(公告)号：US07678625B2

公开(公告)日：2010-03-16

申请号：US11962742

申请日：2007-12-21

申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

IPC分类号： H01L21/84

CPC分类号： H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

摘要翻译： 制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。 单晶半导体层包括从其表面延伸的突起。 在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。 执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。 可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。 还讨论了制造叠层半导体存储器件的相关方法。

公开(公告)号：US07670942B2

公开(公告)日：2010-03-02

申请号：US11525490

申请日：2006-09-23

申请人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

发明人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/7684 ,  H01L27/10873 ,  H01L27/10885

摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

公开(公告)号：US20090137126A1

公开(公告)日：2009-05-28

申请号：US12277332

申请日：2008-11-25

申请人： Yu-Kyung Kim ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Chang-Ki Hong

发明人： Yu-Kyung Kim ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Chang-Ki Hong

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/30617 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/6653

摘要： A sacrificial layer and wet etch are used to form a sidewall spacer so as to prevent damage to the structure on which the spacer is formed and to the underlying substrate as well. Once the structure is formed on the substrate a spacer formation layer is formed to cover the structure, and a sacrificial layer is formed on the spacer formation layer. The sacrificial layer is wet etched to form a sacrificial layer pattern on that portion of the spacer formation layer extending along a sidewall of the structure. The spacer is formed on the sidewall of the structure by wet etching the spacer formation layer using the sacrificial layer pattern as a mask.

摘要翻译： 使用牺牲层和湿蚀刻来形成侧壁间隔物，以便防止对形成间隔物的结构和下面的衬底造成损坏。 一旦在衬底上形成结构，形成间隔物形成层以覆盖该结构，并且在间隔物形成层上形成牺牲层。 对牺牲层进行湿蚀刻以在沿着结构的侧壁延伸的间隔物形成层的该部分上形成牺牲层图案。 通过使用牺牲层图案作为掩模湿蚀刻间隔物形成层，在该结构的侧壁上形成间隔物。

公开(公告)号：US07435644B2

公开(公告)日：2008-10-14

申请号：US11329577

申请日：2006-01-11

申请人： Woo-Gwan Shim ,  Jung-Min Oh ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Sang-Yong Kim

发明人： Woo-Gwan Shim ,  Jung-Min Oh ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Sang-Yong Kim

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： Provided is a method of manufacturing a capacitor of a semiconductor device, which can prevent tilting or an electrical short of a lower electrode. In the method, a mesh-type bridge insulating layer is formed above the contact plug on a mold oxide layer. The mold oxide layer and the bridge insulating layer are etched to define an electrode region. The mold oxide layer is removed using an etching gas having an etch selectivity of 500 or greater for the mold oxide layer with respect to the bridge insulating layer.

摘要翻译： 提供一种制造半导体器件的电容器的方法，其可以防止下电极的倾斜或电短路。 在该方法中，在模具氧化物层上的接触插塞上方形成网状桥接绝缘层。 蚀刻模具氧化物层和桥接绝缘层以限定电极区域。 使用相对于桥接绝缘层的模具氧化物层的蚀刻选择性为500以上的蚀刻气体去除模具氧化物层。

公开(公告)号：US07435301B2

公开(公告)日：2008-10-14

申请号：US11104829

申请日：2005-04-13

申请人： Chang-Sup Mun ,  Doo-Won Kwon ,  Hyung-Ho Ko ,  Chang-Ki Hong ,  Sang-Jun Choi

发明人： Chang-Sup Mun ,  Doo-Won Kwon ,  Hyung-Ho Ko ,  Chang-Ki Hong ,  Sang-Jun Choi

IPC分类号： C23G1/16

CPC分类号： H01L21/02052 ,  C11D1/66 ,  C11D1/72 ,  C11D3/044 ,  C11D11/0047 ,  H01L21/3081 ,  Y10S134/902

摘要： Disclosed are a cleaning solution for preventing damage of a silicon germanium layer when cleaning a semiconductor device including the silicon germanium layer and a cleaning method using the same. The cleaning solution of a silicon germanium layer includes from about 0.01 to about 2.5 percent by weight of a non-ionic surfactant with respect to 100 percent by weight of the cleaning solution, about 0.05 to about 5.0 percent by weight of an alkaline compound with respect to the cleaning solution and a remaining amount of pure water. The damage to an exposed silicon germanium layer can be prevented when cleaning a silicon substrate having a silicon germanium layer. Impurities present on the surface portion of the silicon germanium layer can be effectively removed.

摘要翻译： 公开了一种用于在清洁包括硅锗层的半导体器件时的防止硅锗层损坏的清洁溶液以及使用其的清洁方法。 硅锗层的清洁溶液包括约0.01至约2.5重量％的非离子表面活性剂相对于100重量％的清洁溶液，约0.05至约5.0重量％的碱性化合物，相对于 到清洁溶液和剩余量的纯水。 当清洁具有硅锗层的硅衬底时，可以防止暴露的硅锗层的损坏。 可以有效地除去存在于硅锗层的表面部分上的杂质。

公开(公告)号：US07262141B2

公开(公告)日：2007-08-28

申请号：US11194794

申请日：2005-08-01

申请人： Hyung-Ho Ko ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Dong-Gyun Han

发明人： Hyung-Ho Ko ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Dong-Gyun Han

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/30604 ,  H01L21/0206 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  Y10S438/906

摘要： A method for cleaning a semiconductor substrate forming device isolation layers in a predetermined region of a semiconductor substrate to define active regions; etching predetermined areas of the active regions to form a recess channel region and such that sidewalls of the device isolation layers are exposed; and selectively etching a surface of the recess channel region using a predetermined cleaning solution to clean the semiconductor substrate where the recess channel region has been formed.

摘要翻译： 一种用于清洁在半导体衬底的预定区域中形成器件隔离层的半导体衬底以限定有源区域的方法; 蚀刻有源区域的预定区域以形成凹陷沟道区域，并且使得器件隔离层的侧壁被暴露; 并且使用预定的清洗溶液选择性地蚀刻凹槽通道区域的表面，以清洁已经形成凹槽通道区域的半导体衬底。