公开(公告)号：US10770303B2

公开(公告)日：2020-09-08

申请号：US16397439

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/308 ,  G03F7/20 ,  G03F1/00 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/302 ,  H01L21/033 ,  H01L21/02

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

公开(公告)号：US20200126914A1

公开(公告)日：2020-04-23

申请号：US16721135

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Chih-Tsung Shih

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L21/3213 ,  H01L21/311

Abstract: A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the substrate feature; forming an etch mask over the first material layer; and applying a dynamic-angle (DA) plasma etching process to the first material layer through the etch mask to form a first material feature. Plasma flux of the DA plasma etching process has an angle of incidence with respect to a normal of the first material layer and the angle of incidence changes in a dynamic mode during the DA plasma etching process.

公开(公告)号：US20190341387A1

公开(公告)日：2019-11-07

申请号：US16515709

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/108 ,  H01L27/02 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US10410863B2

公开(公告)日：2019-09-10

申请号：US15852129

申请日：2017-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Wen-Chun Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3213

Abstract: The present disclosure provides a method that includes forming a first pattern feature and a second pattern feature over a material layer by a first photolithographic process. The method also includes forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature. Additionally, the method includes forming a third pattern feature on the material layer between the first spacer feature and the second spacer feature by a second photolithographic process. In addition, the method includes removing the first and second spacer features to expose a portion of the material layer.

公开(公告)号：US10032664B2

公开(公告)日：2018-07-24

申请号：US15174699

申请日：2016-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Chih-Ming Lai ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528 ,  H01L21/3213 ,  H01L23/522

Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.

公开(公告)号：US20170358566A1

公开(公告)日：2017-12-14

申请号：US15668930

申请日：2017-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L23/522 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L27/0207 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0657

Abstract: Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced a first distance from the first target feature, and the third target feature is spaced a second distance from the first target feature. The first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process.

公开(公告)号：US09761436B2

公开(公告)日：2017-09-12

申请号：US14334904

申请日：2014-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/027 ,  H01L21/02 ,  H01L21/308 ,  G03F7/20 ,  G03F1/00 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/302 ,  H01L21/033

CPC classification number: H01L21/02071 ,  G03F1/144 ,  G03F7/70466 ,  H01L21/0337 ,  H01L21/302 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

公开(公告)号：US20170124243A1

公开(公告)日：2017-05-04

申请号：US15357716

申请日：2016-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Kuei-Liang Lu

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G03F1/144 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/06 ,  H01L21/027 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.

公开(公告)号：US20170053870A1

公开(公告)日：2017-02-23

申请号：US14832072

申请日：2015-08-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Chih-Tsung Shih

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/5283 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226

Abstract: A device includes a substrate feature disposed over a substrate. The substrate feature has a first length extending along a first direction and a second length extending along a second direction. The first length is greater than the second length. The device also includes a first material feature disposed over the substrate. The first material feature has a first surface in physical contact with the substrate feature and a second surface opposite to the first surface. The first surface has a third length extending along the first direction and a fourth length extending along the second direction. The third length is greater than the fourth length. The second surface has a fifth length extending along the first direction and a sixth length extending along the second direction. The sixth length is greater than the fifth length.

Abstract translation: 一种器件包括设置在衬底上的衬底特征。 衬底特征具有沿着第一方向延伸的第一长度和沿着第二方向延伸的第二长度。 第一长度大于第二长度。 该装置还包括设置在基板上的第一材料特征。 第一材料特征具有与基底特征物理接触的第一表面和与第一表面相对的第二表面。 第一表面具有沿第一方向延伸的第三长度和沿第二方向延伸的第四长度。 第三长度大于第四长度。 第二表面具有沿第一方向延伸的第五长度和沿第二方向延伸的第六长度。 第六个长度大于第五个长度。

公开(公告)号：US20160203991A1

公开(公告)日：2016-07-14

申请号：US15076199

申请日：2016-03-21

Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.

Inventor： Shih-Ming Chang

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method for forming patterns in a semiconductor device includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; and forming a second feature in a second hard mask layer formed over the patterning-target layer. The first hard mask layer has a different etching selectivity from the second hard mask layer. The method further includes selectively removing a portion of the first feature within a first trench to form a reshaped first feature. In an embodiment, the first trench exposes a portion of the second feature, and the selectively removing of the first portion of the first feature does not etch the portion of the second feature.

Abstract translation: 一种用于在半导体器件中形成图案的方法包括提供在衬底上形成的衬底和图案化目标层; 在形成在所述图案化目标层上的第一硬掩模层中形成第一特征; 以及在形成在图案化目标层上的第二硬掩模层中形成第二特征。 第一硬掩模层具有与第二硬掩模层不同的蚀刻选择性。 该方法还包括选择性地去除第一沟槽内的第一特征的一部分以形成重塑的第一特征。 在一个实施例中，第一沟槽暴露第二特征的一部分，并且选择性地移除第一特征的第一部分不会蚀刻第二特征的部分。