公开(公告)号：US20190293868A1

公开(公告)日：2019-09-26

申请号：US16441785

申请日：2019-06-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Yu Lee ,  Ying-Hao Kuo ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/136 ,  G02B6/42 ,  C09K13/02 ,  H01L21/308 ,  H01L21/306 ,  G02B6/122

Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

公开(公告)号：US20190131240A1

公开(公告)日：2019-05-02

申请号：US16232921

申请日：2018-12-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Lin Teng ,  Jung-Hsun Tsai ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/532 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/768 ,  H01L29/417 ,  H01L29/45 ,  H01L23/528 ,  H01L29/66 ,  H01L23/485 ,  H01L21/283 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/522

Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

公开(公告)号：US10082626B2

公开(公告)日：2018-09-25

申请号：US15342669

申请日：2016-11-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kai-Fang Cheng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L25/16 ,  G02B6/122 ,  G02B6/42 ,  G02B6/24 ,  G02B6/132 ,  H01L21/56 ,  H01L29/06 ,  H01L23/31 ,  G02B6/138 ,  G02B6/136 ,  H01L21/48 ,  G02B6/12

CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/136 ,  G02B6/138 ,  G02B2006/12104 ,  H01L21/48 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3192 ,  H01L29/06 ,  H01L2224/73204

Abstract: A method comprises forming a plateau region and a trench region over a substrate, wherein the trench region comprises a slope and a flat bottom, depositing a reflecting layer over the flat bottom and a portion of the slope, depositing a first adhesion promoter layer over the reflecting layer, applying a first curing process to the first adhesion promoter layer, wherein, after the first curing process finishes, the reflecting layer and the first adhesion promoter layer form a first bonding interface, depositing a bottom cladding layer deposited over the first adhesion promoter layer, applying a second curing process to the bottom cladding layer to form a second bonding interface layer, depositing a core layer over the bottom cladding layer and depositing a top cladding layer over the core layer.

公开(公告)号：US20180188451A1

公开(公告)日：2018-07-05

申请号：US15911403

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/12 ,  G02B6/132 ,  G02B6/136 ,  G02B6/138 ,  F21V8/00 ,  G02B6/42

CPC classification number: G02B6/12004 ,  G02B6/0083 ,  G02B6/132 ,  G02B6/136 ,  G02B6/138 ,  G02B6/4214 ,  G02B2006/12061 ,  G02B2006/12104 ,  G02B2006/12121 ,  G02B2006/12176

Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

公开(公告)号：US20180130752A1

公开(公告)日：2018-05-10

申请号：US15860014

申请日：2018-01-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/322

CPC classification number: H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

公开(公告)号：US20180076132A1

公开(公告)日：2018-03-15

申请号：US15810337

申请日：2017-11-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Hsun Tsai ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Tien-I Bao ,  Chien-Hua Huang

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

公开(公告)号：US09905457B2

公开(公告)日：2018-02-27

申请号：US14583514

申请日：2014-12-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/768 ,  H01L21/02 ,  H01B3/20 ,  H01L23/532

CPC classification number: H01L21/76837 ,  H01B3/20 ,  H01L21/02118 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02282 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/53233 ,  H01L23/5329

Abstract: A method for forming an interconnect structure includes forming a patterned layer over a substrate, the patterned layer having an opening therein. A dielectric material is filled in the opening. The dielectric material has a precursor and a solvent, the solvent having a boiling point temperature greater than a precursor cross-linking temperature. A thermal treatment is performed on the dielectric material to form a dielectric layer.

公开(公告)号：US09881871B2

公开(公告)日：2018-01-30

申请号：US14841346

申请日：2015-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L21/768 ,  H01L21/322 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

公开(公告)号：US20180012761A1

公开(公告)日：2018-01-11

申请号：US15714821

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Chang ,  Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tien-I Bao ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC: H01L21/033 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L21/0338 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/32139

Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

公开(公告)号：US09859152B2

公开(公告)日：2018-01-02

申请号：US15183548

申请日：2016-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes determining a thickness of the protecting layer based on the expected concentration of metal ions. The method also includes forming the protecting layer at the determined thickness and in contact with the dielectric layer. The protecting layer can include at least one of silicon doped nitride, carbon nitride, silicon nitride, or silicon carbon.