公开(公告)号：US20240203749A1

公开(公告)日：2024-06-20

申请号：US18415411

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chia-Cheng Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/32 ,  G03F7/00 ,  H01L21/027

CPC classification number: H01L21/32 ,  G03F7/70283 ,  H01L21/027

Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.

公开(公告)号：US12009305B2

公开(公告)日：2024-06-11

申请号：US18302101

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53242 ,  H01L21/3215 ,  H01L21/76883 ,  H01L23/5226

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

公开(公告)号：US20240096677A1

公开(公告)日：2024-03-21

申请号：US18521314

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/68 ,  G06T1/00 ,  G06T7/00 ,  G06T7/73 ,  H01L23/544

CPC classification number: H01L21/681 ,  G06T1/0014 ,  G06T7/0004 ,  G06T7/73 ,  H01L23/544 ,  G06T2207/30148 ,  H01L2223/54493

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

公开(公告)号：US20240047553A1

公开(公告)日：2024-02-08

申请号：US18150596

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Liang-Yin Chen ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes: forming semiconductor fin structures over a substrate, where each of the semiconductor fin structures includes a layer stack over a semiconductor fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a capping layer over sidewalls and upper surfaces of the semiconductor fin structures; and forming hybrid fins over isolation regions on opposing sides of the semiconductor fin structures, where forming the hybrid fins includes: forming dielectric fins over the isolation regions; and forming dielectric structures over the dielectric fins, which includes: forming an etch stop layer (ESL) over the dielectric fins; doping the ESL with a dopant; and forming a first dielectric material over the doped ESL.

公开(公告)号：US11862694B2

公开(公告)日：2024-01-02

申请号：US17223293

申请日：2021-04-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Shih-Hsiang Chiu ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L21/311 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/40 ,  H01L21/3115

CPC classification number: H01L29/41791 ,  H01L21/28568 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

公开(公告)号：US11854853B2

公开(公告)日：2023-12-26

申请号：US17199980

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/68 ,  H01L23/544 ,  G06T7/73 ,  G06T1/00 ,  G06T7/00

CPC classification number: H01L21/681 ,  G06T1/0014 ,  G06T7/0004 ,  G06T7/73 ,  H01L23/544 ,  G06T2207/30148 ,  H01L2223/54493

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

公开(公告)号：US20230411474A1

公开(公告)日：2023-12-21

申请号：US18366369

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Shih-Hsiang Chiu ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L21/311 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/40 ,  H01L21/3115

CPC classification number: H01L29/41791 ,  H01L27/0924 ,  H01L29/45 ,  H01L29/7851 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/28568 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/401 ,  H01L29/66795

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

公开(公告)号：US20230411156A1

公开(公告)日：2023-12-21

申请号：US18362463

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Chun-Yen Chang ,  Chih-Kai Yang ,  Yu-Tien Shen ,  Ya Hui Chang

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0274 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/31144

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

公开(公告)号：US20230317519A1

公开(公告)日：2023-10-05

申请号：US18330466

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L29/66795

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US20230307525A1

公开(公告)日：2023-09-28

申请号：US18326115

申请日：2023-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Liang-Yin Chen ,  Yi-Hsiu Liu ,  Tsung-Lin Lee ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/66537 ,  H01L29/42324 ,  H01L29/66545 ,  H01L29/4991 ,  H01L29/0649 ,  H01L29/66795 ,  H01L21/823864 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/515 ,  H01L29/6653 ,  H01L29/785 ,  H01L21/02112

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.