利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

343 条记录 (耗时 0.07 秒)

    Non-volatile semiconductor memory device for storing multi-value data
    53.
    发明授权
    Non-volatile semiconductor memory device for storing multi-value data 失效
    用于存储多值数据的非易失性半导体存储器件

    公开(公告)号：US5521865A

    公开(公告)日：1996-05-28

    申请号：US401789

    申请日：1995-03-10

    申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Gertjan Hemink

    发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Gertjan Hemink

    IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： A non-volatile semiconductor memory device having a plurality of electrically rewritable memory cells for storing multi-value data. The cells are arranged in an array and are coupled to a plurality of bit lines which transmit and receive data to and from the memory cells. The device also includes a plurality of sense amplifiers for sensing and amplifying the potentials of the bit lines; a plurality of data latches forming data to be written in the memory cells; a plurality of verify circuits for checking whether the data is correctly written in the memory cells and a plurality of switches. The switches control the connections of the sense amplifiers, data latches and verify circuits to the bit lines. Write control devices set the potentials of the bit lines in accordance with the contents of the data latches. The switches are set in an open state after data is read from the memory cells onto the bit lines and the sense amplifiers almost simultaneously operate after the switches are set in an open state to sense and amplify the data read onto the bit lines.

    摘要翻译： 一种具有用于存储多值数据的多个电可重写存储单元的非易失性半导体存储器件。 单元被布置成阵列并且耦合到多个位线，其向存储器单元发送数据和从存储器单元接收数据。 该器件还包括多个读出放大器，用于感测和放大位线的电位; 多个数据锁存器，形成要写入存储单元的数据; 用于检查数据是否正确写入存储单元的多个验证电路和多个开关。 开关控制读出放大器，数据锁存器和验证电路到位线的连接。 写控制装置根据数据锁存器的内容设置位线的电位。 在将数据从存储器单元读取到位线上之后，开关被设置为打开状态，并且在开关被设置为打开状态之后，读出放大器几乎同时工作，以感测和放大读取到位线上的数据。

    Nonvolatile semiconductor memory apparatus
    54.
    发明授权
    Nonvolatile semiconductor memory apparatus 失效
    非易失性半导体存储装置

    公开(公告)号：US5477495A

    公开(公告)日：1995-12-19

    申请号：US225926

    申请日：1994-04-11

    申请人： Yoshiyuki Tanaka ,  Tomoharu Tanaka ,  Koji Sakui ,  Hiroshi Nakamura ,  Kazunori Ohuchi ,  Hideko Oodaira ,  Yutaka Okamoto

    发明人： Yoshiyuki Tanaka ,  Tomoharu Tanaka ,  Koji Sakui ,  Hiroshi Nakamura ,  Kazunori Ohuchi ,  Hideko Oodaira ,  Yutaka Okamoto

    IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C7/00

    CPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/28

    摘要： A nonvolatile semiconductor memory apparatus of the present invention has a feature that charging of a control gate of a nonselective memory cell is simultaneously executed upon charging of a bit line. That is, in the case of normal reading (random accessing), charging of the control gate of the nonselective memory cell is conducted previously to at least one of source and drain side selective gates. Then, when the threshold value of the memory cell in the case of erasing the cell is judged, in a read mode, charging of the selective gate is started by delaying from the timing of charging the control gate of the nonselective memory cell to negative. That is, the selective gate is closed until the control gate is completely set to a negative testing voltage to prevent the bit line from being discharged. After the control gate is completely set to the negative testing voltage, the selective gate is delayed to be charged so that the selective gate is turned ON.

    摘要翻译： 本发明的非易失性半导体存储装置的特征在于，在对位线进行充电时，同时执行非选择性存储单元的控制栅极的充电。 也就是说，在正常读取（随机存取）的情况下，预选择非选择性存储单元的控制栅极的充电至源极和漏极侧选择栅极中的至少一个。 然后，当在读取模式中判断在擦除单元的情况下存储单元的阈值时，通过从非选择性存储单元的控制栅极的充电时间延迟到负极来开始选择栅极的充电。 也就是说，选择栅极闭合，直到控制栅极完全设置为负的测试电压，以防止位线被放电。 在控制栅极完全设置为负测试电压之后，选择栅极被延迟以被充电，使得选择栅极导通。

    Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels
    55.
    发明授权
    Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
    具有写入验证控制器的电可擦除和可编程非易失性存储器系统，使用两个参考电平

    公开(公告)号：US5469444A

    公开(公告)日：1995-11-21

    申请号：US341955

    申请日：1994-11-16

    申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

    发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

    IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

    摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

    摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

    Electrically erasable programmable read-only memory with write/verify controller
    56.
    发明授权
    Electrically erasable programmable read-only memory with write/verify controller 失效
    具有写/验证控制器的电可擦除可编程只读存储器

    公开(公告)号：US5379256A

    公开(公告)日：1995-01-03

    申请号：US223307

    申请日：1994-04-05

    申请人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

    发明人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

    IPC分类号： G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C7/00

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C7/067

    摘要： A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.

    摘要翻译： 多个电可擦除可编程只读存储器或EEPROM与控制器LSI相关联。 每个EEPROM包括以行和列排列的浮栅隧穿存储单元晶体管阵列。 当选择提供单页数据的存储单元晶体管的子阵列进行编程时，控制器LSI通过检查所选存储单元晶体管的阈值来验证所选择的存储单元晶体管的编程之后，如下进行写入/校验操作 变化的值，并且当任何潜在的不足的单元晶体管保持在其中之间时，重复使用预定时间段的预定写入电压的重写操作，使得所得到的写入状态可能更接近可满足的参考状态。 通过将写入电压施加到不足的单元晶体管预定时间段来执行每个重写/验证操作。

    Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller
    58.
    发明授权
    Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
    具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器

    公开(公告)号：US5357462A

    公开(公告)日：1994-10-18

    申请号：US948002

    申请日：1992-09-21

    申请人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Hiroshi Nakamura ,  Hideko Odaira

    发明人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Hiroshi Nakamura ,  Hideko Odaira

    IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/02

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3454

    摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.

    摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。 每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。 感测/锁存电路连接到位线，并且有选择地执行写数据的检测操作和锁存操作。 提供了一种程序控制器，用于将数据写入指定区域中的所选择的存储单元中，并且用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。 如果不足，则重写数据。 提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并将写入数据锁存在感测/锁存电路中，并且自动更新存储在感测/锁存器中的重写数据 根据实际写入状态对每个位线进行电路验证。 感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

    NAND-cell type electrically erasable and programmable read-only memory with redundancy circuit
    59.
    发明授权
    NAND-cell type electrically erasable and programmable read-only memory with redundancy circuit 失效
    具有冗余电路的NAND单元型电可擦除可编程只读存储器

    公开(公告)号：US5278794A

    公开(公告)日：1994-01-11

    申请号：US960882

    申请日：1992-10-14

    申请人： Yoshiyuki Tanaka ,  Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka

    发明人： Yoshiyuki Tanaka ,  Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka

    IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40 ,  G11C5/02

    CPC分类号： G11C29/789 ,  G11C16/0483 ,  G11C29/808 ,  G11C29/82

    摘要： A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and an insulated control gate. The memory cell array is divided into a plurality of cell blocks, each of which includes NAND cell sections each including a predetermined number of a series-connected memory cell transistors. A redundancy cell section is provided which includes an array of redundancy memory cells containing at least one spare cell block. A row redundancy circuit is connected to a row decoder, and is responsive to an address buffer. The redundancy circuit replaces a defective block containing a defective memory cell or cells with the spare cell block.

    摘要翻译： NAND单元型电可擦除和可编程只读存储器包括与半导体基板上的并行位线相关联的存储单元的行和列阵列。 每个存储单元基本上由具有浮置栅极和绝缘控制栅极的浮栅场效应晶体管组成。 存储单元阵列被分成多个单元块，每个单元块包括每个包括预定数量的串联存储单元晶体管的NAND单元部分。 提供冗余单元部分，其包括包含至少一个备用单元块的冗余存储单元的阵列。 行冗余电路连接到行解码器，并响应于地址缓冲器。 冗余电路用备用单元块替代含有缺陷存储单元或单元的缺陷块。