公开(公告)号：US10199381B2

公开(公告)日：2019-02-05

申请号：US15637462

申请日：2017-06-29

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L27/11 ,  H01L21/225 ,  H01L21/324 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

摘要： An SRAM includes three Si pillars. In upper parts of the Si pillars, a first load P-channel, a first driver N-channel, and a first selection N-channel are formed, and in lower parts of the Si pillars, a second load P-channel, a second driver N-channel, and a second selection N-channel are formed. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the second load P-channel and the second driver N-channel. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the first load P-channel and the first driver N-channel. Gates surrounding the first and second selection N-channels are connected to a word-line terminal.

公开(公告)号：US10002934B2

公开(公告)日：2018-06-19

申请号：US14602729

申请日：2015-01-22

申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

发明人： Fujio Masuoka ,  Nozomu Harada ,  Hiroki Nakamura

IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L29/08 ,  H01L27/02

CPC分类号： H01L29/42392 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/16 ,  H01L29/7827

摘要： A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

公开(公告)号：US09865535B2

公开(公告)日：2018-01-09

申请号：US15346176

申请日：2016-11-08

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Nozomu Harada

IPC分类号： H01L29/66 ,  H01L23/522 ,  H01L29/423 ,  H01L29/786 ,  H01L27/11 ,  H01L23/532

CPC分类号： H01L23/5228 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78642

摘要： A semiconductor device includes a planar interconnection layer formed on a substrate and made of a semiconductor, a first pillar-shaped semiconductor layer formed on the interconnection layer, a semiconductor-metal compound layer formed so as to cover the entire upper surface of the interconnection layer except for a bottom portion of the first pillar-shaped semiconductor layer, a first gate insulating film surrounding the first pillar-shaped semiconductor layer, a first gate electrode surrounding the first gate insulating film, and a first gate line connected to the first gate electrode.

公开(公告)号：US09589973B2

公开(公告)日：2017-03-07

申请号：US15221215

申请日：2016-07-27

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L27/115 ,  H01L27/112 ,  H01L23/535 ,  G11C16/14

CPC分类号： H01L27/115 ,  G11C16/14 ,  H01L23/535 ,  H01L27/11293 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A pillar-shaped semiconductor memory device includes a silicon pillar, and a tunnel insulating layer, a data charge storage insulating layer, a first interlayer insulating layer, and a first conductor layer, which surround an outer periphery of the silicon pillar in that order, and a second interlayer insulating layer that is in contact with an upper surface or a lower surface of the first conductor layer. A side surface of the second interlayer insulating layer facing a side surface of the first interlayer insulating layer is separated from the side surface of the first interlayer insulating layer with a distance therebetween, the distance being larger than a distance from the side surface of the first interlayer insulating layer to a side surface of the first conductor layer facing the side surface of the first interlayer insulating layer.

摘要翻译： 柱状半导体存储器件包括依次包围硅柱的外周的硅柱和隧道绝缘层，数据电荷存储绝缘层，第一层间绝缘层和第一导体层， 以及与第一导体层的上表面或下表面接触的第二层间绝缘层。 第二层间绝缘层的与第一层间绝缘层的侧面相对的侧面与第一层间绝缘层的侧面隔开间隔开，距离比第一层间绝缘层的侧面的距离大 层间绝缘层连接到第一导体层的与第一层间绝缘层的侧表面相对的侧表面。

公开(公告)号：US09490362B2

公开(公告)日：2016-11-08

申请号：US14744890

申请日：2015-06-19

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada ,  Hiroki Nakamura ,  Yisuo Li ,  Aashit Ramachandra Kamath ,  Zhixian Chen ,  Teng Soong Phua ,  Xinpeng Wang ,  Patrick Guo-Qiang Lo

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28061 ,  H01L21/28238 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/423 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/7827

摘要： A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.

摘要翻译： 半导体器件制造方法包括在硅衬底上形成平面硅层并在平面硅层上形成第一和第二柱状硅层的第一步骤; 在第一和第二柱状硅层周围形成栅极绝缘膜的第二步骤，在栅极绝缘膜周围形成金属膜和多晶硅膜，控制多晶硅膜的厚度小于一半的距离 在第一和第二柱状硅层之间沉积抗蚀剂，将多晶硅膜暴露在第一和第二柱状半导体层的上部的侧壁上，蚀刻掉暴露的多晶硅膜，剥离第三抗蚀剂，以及 蚀刻掉金属膜; 以及形成用于形成栅极线的抗蚀剂并进行各向异性蚀刻以形成栅极线和第一和第二栅电极的第三步骤。

公开(公告)号：US20150287821A1

公开(公告)日：2015-10-08

申请号：US14735275

申请日：2015-06-10

申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

发明人： Fujio Masuoka ,  Nozomu Harada ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC分类号： H01L29/7827 ,  H01L21/28008 ,  H01L21/31116 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66666

摘要： A semiconductor device includes a P+ region and an N+ region functioning as sources of SGTs and disposed in top portions of Si pillars formed on an i-layer substrate. Connections between a power supply wiring metal layer and the P+ region and between a ground wiring metal layer and the N+ region are established on the entire surfaces of low-resistance Ni silicide layers that are respectively in contact with the P+ region and the N+ region and formed on outer peripheries of the Si pillars. Lower ends of the power supply wiring metal layer and the ground wiring metal layer are located at a height of surfaces of HfO layers near the boundaries between the P+ region and a channel and between the N+ region and a channel, respectively.

摘要翻译： 半导体器件包括作为SGT源的P +区和N +区，并且设置在形成在i层衬底上的Si柱的顶部。 在分别与P +区域和N +区域接触的低电阻Ni硅化物层的整个表面上建立电源布线金属层与P +区域之间以及接地布线金属层与N +区域之间的连接， 形成在Si柱的外围。 电源布线金属层和接地布线金属层的下端分别位于P +区域和沟道之间以及N +区域和沟道之间的边界附近的HfO层的表面的高度。

公开(公告)号：US09111794B2

公开(公告)日：2015-08-18

申请号：US14499935

申请日：2014-09-29

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L21/336 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L27/1116 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/16 ,  H01L29/42324 ,  H01L29/66666 ,  H01L29/66825

摘要： In a method for producing a semiconductor device, Si pillars that include i-layers, N+ regions that serve as lower impurity regions, N+ regions and a P+ region that serve as upper impurity regions, and i-layers are formed by using SiO2 layers as an etching mask. Thus, surrounding gate MOS transistors (SGTs) are produced in which the upper impurity regions and the lower impurity regions respectively function as impurity layers constituting a source or a drain of the SGTs formed in upper portions and lower portions of the Si pillars.

摘要翻译： 在制造半导体器件的方法中，包括i层的Si柱，用作低杂质区的N +区，用作上部杂质区的N +区和P +区以及i层通过使用SiO 2层作为 蚀刻掩模 因此，制造周边栅极MOS晶体管（SGT），其中上部杂质区域和下部杂质区域分别用作形成在Si支柱的上部和下部中的SGT的源极或漏极的杂质层。

公开(公告)号：US09082838B2

公开(公告)日：2015-07-14

申请号：US14036554

申请日：2013-09-25

申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

发明人： Fujio Masuoka ,  Nozomu Harada ,  Hiroki Nakamura ,  Navab Singh ,  Zhixian Chen ,  Aashit Ramachandra Kamath ,  Xinpeng Wang

IPC分类号： H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/78 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/66477 ,  H01L29/66666 ,  H01L29/7827

摘要： In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.

摘要翻译： 在第一步骤中，在硅衬底上形成平面硅层，在平面硅层上形成第一和第二柱状硅层; 第二步骤包括在第一和第二柱状硅层上形成氧化膜硬掩模，在平坦硅层上形成第二氧化膜，第二氧化物膜比栅极绝缘膜厚; 并且第三步骤包括在所述第一柱状硅层和所述第二柱状硅层周围形成所述栅极绝缘膜，在所述栅极绝缘膜周围形成金属膜和多晶硅膜，所述多晶硅膜的厚度为 小于第一柱状硅层和第二柱状硅层之间的距离的一半，形成用于形成栅极线的第三抗蚀剂，并进行各向异性蚀刻以形成栅极线。

公开(公告)号：US08836051B2

公开(公告)日：2014-09-16

申请号：US13908125

申请日：2013-06-03

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada ,  Hiroki Nakamura ,  Xiang Li ,  Xinpeng Wang ,  Zhixian Chen ,  Aashit Ramachandra Kamath ,  Navab Singh

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/423

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78642

摘要： A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.

摘要翻译： 一种制造半导体器件的方法包括：第一步骤，包括形成平面硅层并形成第一和第二柱状硅层; 第二步骤包括在所述第一和第二柱状硅层的每一个周围形成栅极绝缘膜，在所述栅极绝缘膜周围形成金属膜和多晶硅膜，所述多晶硅膜的厚度小于所述多晶硅膜的厚度的一半， 第一和第二柱状硅层，形成第三抗蚀剂，并形成栅极线; 以及第三步骤，包括沉积第四抗蚀剂，使得第一和第二柱状硅层中的每一个的上侧壁上的多晶硅膜的一部分露出，去除多晶硅膜的暴露部分，除去第四抗蚀剂 并且去除金属膜以形成第一和第二栅电极。

公开(公告)号：US12131773B2

公开(公告)日：2024-10-29

申请号：US18080021

申请日：2022-12-13

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Koji Sakui ,  Riichiro Shirota ,  Nozomu Harada

IPC分类号： G11C11/24 ,  G11C11/4094 ,  G11C11/4096 ,  G11C16/24 ,  H10B12/00

CPC分类号： G11C11/4096 ,  G11C11/4094 ,  G11C16/24 ,  H10B12/20 ,  G11C2211/401

摘要： A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.