公开(公告)号：US20170062349A1

公开(公告)日：2017-03-02

申请号：US14836947

申请日：2015-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chiao Wang ,  Yu-Hsiang Hung ,  Chao-Hung Lin ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L23/544 ,  H01L21/311 ,  H01L21/033 ,  H01L21/28

CPC classification number: H01L23/544 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28132 ,  H01L21/32139 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供了包括晶片和对准标记的半导体结构。 晶片具有切割区域，其包括中心区域，中间区域围绕中心区域，周边区域围绕中间区域。 对准标记设置在切割区域中，其中对准标记是镜像对称图案。 对准标记包括中间区域中的多个第二图案和设置在周边区域中的多个第三图案，其中每个第三图案包括多条线，并且该线的宽度比L的宽度小10倍 形状。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09583394B2

公开(公告)日：2017-02-28

申请号：US15293292

申请日：2016-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L21/324 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/308 ,  H01L27/092 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.

Abstract translation: 本发明提供一种半导体结构的形成方法，其特征在于，首先，设置具有第一鳍结构和设置在其上的第二鳍结构的衬底，接着，在所述第一鳍结构和所述第二鳍结构之间形成第一隔离区 鳍结构，与第一隔离区相对地形成第二隔离区，并且在第一鳍结构和第二鳍结构的一侧形成至少外延层，其中外延层具有底表面 所述底表面从所述第一鳍结构延伸到所述第二鳍结构，并且所述底表面低于所述第一隔离区域的底表面和所述第二隔离区域的顶表面，此外，所述外延层具有阶梯状 形侧壁轮廓。

公开(公告)号：US20170005102A1

公开(公告)日：2017-01-05

申请号：US14816081

申请日：2015-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L27/11 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有第一区域，第二区域和第三区域的衬底; 在所述第一区域，所述第二区域和所述第三区域上形成多个间隔物; 形成第一图案化掩模以覆盖第一区域和第二区域上的间隔物; 并移除第三区域上的间隔物。

公开(公告)号：US09484263B1

公开(公告)日：2016-11-01

申请号：US14926003

申请日：2015-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate, a first hard mask disposed on the first gate and a first spacer surrounding the first gate and the first hard mask, wherein the second gate structure includes a second gate, a second hard mask disposed on the second gate and a second spacer surrounding the second gate and the second hard mask. Later, the first spacer surrounding the first hard mask and the second spacer surrounding the second hard mask are removed. After that, a dielectric layer is formed to cover the first hard mask and the second hard mask. Finally, the second dielectric layer, the first mask layer and the second mask layer are removed.

Abstract translation: 去除栅极上的硬掩模的方法包括形成第一栅极结构和第二栅极结构。 第一栅极结构包括第一栅极，设置在第一栅极上的第一硬掩模和围绕第一栅极和第一硬掩模的第一隔离物，其中第二栅极结构包括第二栅极，设置在第二栅极上的第二硬掩模 栅极和围绕第二栅极和第二硬掩模的第二隔板。 随后，围绕第一硬掩模的第一间隔物和围绕第二硬掩模的第二间隔物被去除。 之后，形成介电层以覆盖第一硬掩模和第二硬掩模。 最后，去除第二电介质层，第一掩模层和第二掩模层。

公开(公告)号：US20160218179A1

公开(公告)日：2016-07-28

申请号：US14634904

申请日：2015-03-02

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Shih-Fang Hong ,  Chao-Hung Lin ,  Jyh-Shyang Jenq

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L21/02603 ,  H01L21/823807 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: A nanowire transistor device includes a substrate, a plurality of nanowires formed on the substrate, and a gate surrounding at least a portion of each nanowire. The nanowires respectively include a first semiconductor core and a second semiconductor core surrounding the first semiconductor core. A lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core.

Abstract translation: 纳米线晶体管器件包括衬底，形成在衬底上的多个纳米线和围绕每个纳米线的至少一部分的栅极。 纳米线分别包括第一半导体芯和围绕第一半导体芯的第二半导体芯。 第二半导体芯的晶格常数与第一半导体芯的晶格常数不同。

公开(公告)号：US20160190287A1

公开(公告)日：2016-06-30

申请号：US14607085

申请日：2015-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Chao-Hung Lin ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.

Abstract translation: 形成半导体器件的方法包括以下步骤。 首先，提供具有晶体管的衬底，其中晶体管包括源极/漏极区域。 在基板上形成电介质层，并且在电介质层中形成接触插塞以电连接源极/漏极区域。 接下来，在电介质层上形成掩模层，其中掩模层包括第一层和堆叠在其上的第二层。 之后，在掩模层的第二层上形成槽切割图案，并且在掩模层的第一层上形成接触槽图案。 最后，通过使用第一层上的接触槽图案，去除第二层并形成接触开口。

公开(公告)号：US09349653B2

公开(公告)日：2016-05-24

申请号：US14539225

申请日：2014-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Chih-Sen Huang ,  Li-Wei Feng ,  Jyh-Shyang Jenq

IPC: H01L21/8228 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/76847 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.

Abstract translation: 提供一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供基板。 在基板上形成翅片结构和层间电介质层。 在基板上形成多个栅极结构。 在栅极结构上形成盖层。 在盖层上形成硬掩模。 在硬掩模上形成覆盖栅极结构的第一图案化光致抗蚀剂层。 硬掩模被蚀刻和图案化以形成图案化的硬掩模，使得图案化的硬掩模覆盖栅极结构。 在图案化的硬掩模上形成包括对应于鳍结构的多个开口的第二图案化光致抗蚀剂层。 蚀刻覆盖层和层间电介质层以形成暴露鳍结构的一部分的多个第一沟槽。

公开(公告)号：US20160111448A1

公开(公告)日：2016-04-21

申请号：US14519146

申请日：2014-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/76202 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供了至少具有翅片结构的基板。 衬垫形成在翅片结构的侧壁上。 在翅片结构和基板之间形成氧化物层。 排除翅片结构，直到翅片结构的底层被保留，以在衬垫之间形成凹陷。 在凹部中依次形成缓冲外延层和外延层。 去除衬里的顶部，直到露出外延层的侧壁。 此外，还提供了通过所述方法形成的鳍状结构。

公开(公告)号：US09287263B1

公开(公告)日：2016-03-15

申请号：US14537840

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966

Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 该方法首先包括衬底，并且在衬底上形成第一半导体器件和第二半导体器件，分别具有第一栅极沟槽和第二沟槽。 接下来，在第一栅极沟槽和第二沟槽中形成底部阻挡层。 之后，执行第一回拉步骤以去除底部阻挡层的部分，然后在第一栅极沟槽中形成第一功函数金属层。 接下来，执行第二拉回步骤以去除第一功函数金属层的部分，其中第一功函数金属层的最顶部比第一栅沟槽和第二栅沟的开口低。

公开(公告)号：US11948975B2

公开(公告)日：2024-04-02

申请号：US17509061

申请日：2021-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/665

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.