公开(公告)号：US20210119115A1

公开(公告)日：2021-04-22

申请号：US17134460

申请日：2020-12-27

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC分类号： H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

摘要： A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US10854520B2

公开(公告)日：2020-12-01

申请号：US16416279

申请日：2019-05-20

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Chun-Hsien Lin ,  Wei-Hao Huang ,  Kai-Teng Cheng

IPC分类号： H01L21/8234 ,  H01L21/321 ,  H01L21/28 ,  H01L21/30 ,  H01L27/092 ,  H01L21/8238

摘要： The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

公开(公告)号：US10109525B1

公开(公告)日：2018-10-23

申请号：US15820123

申请日：2017-11-21

申请人： United Microelectronics Corp.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Jiunn-Hsiung Liao ,  Wei-Hao Huang ,  Kai-Teng Cheng

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L29/78

摘要： A method for fabricating a semiconductor device is provided including providing a substrate, on which a plurality of elements is formed. A first inter-dielectric layer is formed over the substrate, covering the elements. A first plug structure is formed in the first inter-dielectric layer, including performing a polishing process over the first inter-dielectric layer to have a dishing on top and extending from a sidewall of the first plug structure. A hard mask layer is formed to fill the dishing. A second inter-dielectric layer is formed over the hard mask layer. A second plug structure is formed in the second inter-dielectric layer to electrically contact the first plug structure, wherein the second plug structure has at least an edge portion extending on the hard mask layer.

公开(公告)号：US20180166441A1

公开(公告)日：2018-06-14

申请号：US15825057

申请日：2017-11-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/768

CPC分类号： H01L27/0629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L28/20 ,  H01L28/24

摘要： A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

公开(公告)号：US09748349B2

公开(公告)日：2017-08-29

申请号：US14723467

申请日：2015-05-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Wei-Hao Huang

IPC分类号： H01L29/423 ,  H01L21/768 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L29/42364 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/51 ,  H01L29/518 ,  H01L29/785

摘要： A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.

公开(公告)号：US09685531B2

公开(公告)日：2017-06-20

申请号：US15263349

申请日：2016-09-12

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/66628

摘要： A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.

公开(公告)号：US20170125291A1

公开(公告)日：2017-05-04

申请号：US15404163

申请日：2017-01-11

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC分类号： H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

公开(公告)号：US20170077031A1

公开(公告)日：2017-03-16

申请号：US14882424

申请日：2015-10-13

申请人： United Microelectronics Corp.

发明人： Chia-Lin Lu ,  Chun-Hsien Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC分类号： H01L23/535 ,  H01L29/06 ,  H01L29/165 ,  H01L21/265 ,  H01L29/24 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

CPC分类号： H01L29/66795 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

摘要翻译： 半导体器件及其制造方法，半导体器件包括鳍状结构，栅极结构，外延层，锗层，层间介电层和第一插塞。 鳍状结构设置在基板上。 栅极结构跨过鳍状结构形成。 外延层设置在与栅极结构相邻的鳍状结构中。 锗层设置在外延层上。 层间绝缘层覆盖基板和翅片形结构。 第一插头设置在层间电介质层中以与锗层接触。

公开(公告)号：US09385206B2

公开(公告)日：2016-07-05

申请号：US14919738

申请日：2015-10-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Jian-Cun Ke ,  Chun-Lung Chen ,  Lung-En Kuo

IPC分类号： H01L29/76 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/495 ,  H01L21/28088 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

摘要翻译： 公开了一种半导体器件。 半导体器件包括衬底，衬底上的栅极结构和与栅极结构相邻的间隔物，其中间隔物的底部包括锥形轮廓，并且锥形轮廓包括凸曲线。

公开(公告)号：US20160172300A1

公开(公告)日：2016-06-16

申请号：US14591936

申请日：2015-01-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构上形成牺牲层; 在牺牲层和ILD层中形成第一接触塞; 去除牺牲层; 以及在所述栅极结构和所述第一接触插塞上形成第一电介质层。