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    Trace reuse
    51.
    发明申请
    Trace reuse 审中-公开
    跟踪重用

    公开(公告)号：US20060036834A1

    公开(公告)日：2006-02-16

    申请号：US10917582

    申请日：2004-08-13

    Applicant: Subramaniam Maiyuran ,  Peter Smith ,  Varghese George ,  Eran Altshuler ,  Robert Valentine ,  Zeev Offen ,  Oded Lempel

    Inventor： Subramaniam Maiyuran ,  Peter Smith ,  Varghese George ,  Eran Altshuler ,  Robert Valentine ,  Zeev Offen ,  Oded Lempel

    IPC: G06F9/30

    CPC classification number: G06F9/3808 ,  G06F9/325

    Abstract: A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during a period of operation of the microprocessor, avoiding performance gaps due to multiple trace cache accesses and increasing the rate at which uops can be executed within a processor.

    Abstract translation: 一种跟踪管理架构，可以在一个或多个重复轨迹中重新使用uops。 更具体地，本发明的实施例涉及通过重复使用在微处理器的操作期间重复的迹线或迹线序列来防止对跟踪管理架构内的各种功能单元的多次访问的技术，从而避免由于多个跟踪而导致的性能差距 高速缓存访​​问并增加可以在处理器内执行uop的速率。

    Multiple operating frequencies in a processor
    52.
    发明授权
    Multiple operating frequencies in a processor 有权
    处理器中的多个工作频率

    公开(公告)号：US06785829B1

    公开(公告)日：2004-08-31

    申请号：US09608160

    申请日：2000-06-30

    Applicant: Varghese George ,  Robert L. Farrell

    Inventor： Varghese George ,  Robert L. Farrell

    IPC: G06F132

    CPC classification number: G06F1/3296 ,  G06F1/08 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is connected to an external power source. As a result, the electronic device in the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage in some sections of the processor and not in the other sections during other situations.

    Abstract translation: 一种功率控制电路，用于在单个电子设备的部分中调节工作频率和/或电源电压，同时在电子设备中的其它部分保持基本恒定的工作频率和/或电源电压的相应技术。 这种控制是基于通过确定硬件产品是否连接到外部电源的采用电子设备的硬件产品的操作环境。 结果，硬件产品中的电子设备能够在某些情况下以全频率和电压工作，并且在处理器的某些部分中以不降低的频率和/或电压工作，而在其他情况下不在其他部分。

    Deferred correction of a single bit storage error in a cache tag array
    54.
    发明授权
    Deferred correction of a single bit storage error in a cache tag array 失效
    缓存标记数组中单位存储错误的延迟校正

    公开(公告)号：US06502218B1

    公开(公告)日：2002-12-31

    申请号：US09461243

    申请日：1999-12-16

    Applicant: Varghese George ,  Michael Robert Mroczek

    Inventor： Varghese George ,  Michael Robert Mroczek

    IPC: G11C2900

    CPC classification number: G06F11/1064

    Abstract: Methods and apparatus defer correction of an error in a tag entry of a cache tag array. An address of requested data, including an address tag field, can be received by a cache. A first hit indication based at least in part on a comparison of the address tag field and a first tag entry can be generated and result in outputting of a first data entry of a data array. An error in the tag entry can be detected, and the first data entry can be disregard based at least in part on the detected error.

    Abstract translation: 方法和装置延迟缓存标签数组的标签条目中的错误的校正。 高速缓存可以接收包括地址标签字段在内的所请求数据的地址。 可以生成至少部分地基于地址标签字段和第一标签条目的比较的第一命中指示，并且导致数据阵列的第一数据条目的输出。 可以检测到标签条目中的错误，并且至少部分地基于检测到的错误可以忽略第一数据条目。

    COMMON PLATFORM FOR ONE-LEVEL MEMORY ARCHITECTURE AND TWO-LEVEL MEMORY ARCHITECTURE
    57.
    发明申请
    COMMON PLATFORM FOR ONE-LEVEL MEMORY ARCHITECTURE AND TWO-LEVEL MEMORY ARCHITECTURE 有权
    一级存储器架构和两级存储器架构的通用平台

    公开(公告)号：US20150178204A1

    公开(公告)日：2015-06-25

    申请号：US14140261

    申请日：2013-12-24

    Applicant: Joydeep Ray ,  Varghese George ,  Inder M. Sodhi ,  Jeffrey R. Wilcox

    Inventor： Joydeep Ray ,  Varghese George ,  Inder M. Sodhi ,  Jeffrey R. Wilcox

    IPC: G06F12/08 ,  G06F12/06 ,  G06F12/02

    CPC classification number: G06F3/061 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0811 ,  G06F15/781 ,  G06F2212/283 ,  G06F2212/7206 ,  G11C5/04

    Abstract: Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.

    Abstract translation: 描述了在一个通用平台中的一级存储器（1LM）和两级存储器（2LM）配置的技术。 处理器包括耦合到第一存储器设备的第一存储器接口，所述第一存储器设备位于处理器的外部封装处，以及耦合到位于处理器的封装外的第二存储器设备的第二存储器接口。 处理器还包括耦合到第一存储器接口和第二存储器接口的多级存储器控制器（MLMC）。 MLMC包括第一配置和第二配置。 第一存储器件是第一配置中的一级存储器（1LM）架构的随机存取存储器（RAM）。 第一存储器件是第二配置中的二级存储器（2LM）架构的第一级RAM，并且第二存储器件是第二配置中的2LM架构的二级非易失性存储器（NVM）。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING IMPROVED PROCESSOR CORE DEEP POWER DOWN EXIT LATENCY BY USING REGISTER SECONDARY UNINTERRUPTED POWER SUPPLY
    59.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING IMPROVED PROCESSOR CORE DEEP POWER DOWN EXIT LATENCY BY USING REGISTER SECONDARY UNINTERRUPTED POWER SUPPLY 有权
    方法，装置和能源节约系统，其中包括使用注册次级不间断电源改进处理器核心深度断电退出

    公开(公告)号：US20120166852A1

    公开(公告)日：2012-06-28

    申请号：US13335880

    申请日：2011-12-22

    Applicant: Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev S. Jahagirdar ,  Varghese George

    Inventor： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev S. Jahagirdar ,  Varghese George

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D10/172

    Abstract: Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.

    Abstract translation: 本发明的实施例涉及从计算设备处理器核心深度掉电来改善退出等待时间。 处理器状态数据可以在深度掉电模式期间通过提供第二不间断电压供应来始终保持驻留在处理器的关键状态寄存器内的保持器电路。 当这些寄存器接收到指示处理器电源状态将从活动处理器电源状态降低到零处理器电源状态的控制信号时，它们将临界状态数据从临界状态寄存器锁存器写入到所提供的保持器电路 不间断的电源。 然后，当寄存器接收到指示处理器的处理器电源状态将增加回到活动处理器功率状态的控制信号时，存储在保持器电路中的临界状态数据被写回到临界状态寄存器锁存器。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE
    60.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE 有权
    能源效率和能源保护的方法，装置和系统，包括能源效率处理器使用深度掉电模式的热力

    公开(公告)号：US20120166839A1

    公开(公告)日：2012-06-28

    申请号：US13335831

    申请日：2011-12-22

    Applicant: Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    Inventor： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    IPC: G06F1/32

    CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/16 ,  Y02D10/171

    Abstract: Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.

    Abstract translation: 本发明的实施例涉及使用零电压处理器状态的电子设备处理器的节能和节省热节流。 例如，处理器管芯可以包括功率控制单元（PCU）和具有电源门和热传感器的执行单元。 PCU连接到热传感器，以确定执行单元的温度是否已经增加到大于上限阈值，例如当执行单元处理处于活动处理器电源状态的数据时。 PCU也连接到电源门，因此在这种检测时，它可以将主处理器的电源状态改变到零处理器电源状态，以降低执行单元的温度。 当传感器检测到温度降低到低于下限阈值时，PCU可以将处理器电源状态改变回活动状态。

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