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414 条记录 (耗时 0.029 秒)

    Calibration of impedance
    51.
    发明授权
    Calibration of impedance 有权
    阻抗校准

    公开(公告)号：US08937488B2

    公开(公告)日：2015-01-20

    申请号：US14266217

    申请日：2014-04-30

    申请人： PS4 Luxco S.a.r.l.

    发明人： Yoshiro Riho

    IPC分类号： H03K17/16 ,  H03K19/00

    CPC分类号： H03K19/0005 ,  H03K19/018521 ,  H04L25/0278

    摘要： A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

    摘要翻译： 半导体器件具有第一受控芯片，包括具有与第一输出电路相同的配置的第一复制输出电路，连接到第一复制输出电路的第一ZQ端子，连接到第一ZQ端子的第一通电极和 第一控制电路，其设置第一复制输出电路的阻抗。 控制芯片包括连接到第一贯通电极的第二ZQ端子，将第二ZQ端子的电压与参考电压进行比较的比较器电路，以及基于比较器电路进行比较的处理的第二控制电路123 。 第一控制电路和第二控制电路接收公共输入信号以操作并顺序地改变和设置阻抗，直到当外部电阻元件连接到第二ZQ端子时比较结果改变。

    Semiconductor device having plural memory chip
    52.
    发明授权
    Semiconductor device having plural memory chip 有权
    具有多个存储芯片的半导体器件

    公开(公告)号：US08924903B2

    公开(公告)日：2014-12-30

    申请号：US13288631

    申请日：2011-11-03

    申请人： Akira Ide

    发明人： Akira Ide

    IPC分类号： G06F17/50 ,  G11C5/04 ,  H01L25/065 ,  H01L23/48

    CPC分类号： H01L25/0657 ,  G11C5/04 ,  G11C11/408 ,  H01L23/481 ,  H01L23/50 ,  H01L2224/16145 ,  H01L2225/06544

    摘要： A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.

    摘要翻译： 半导体器件包括堆叠的多个存储器芯片。 存储器芯片各自包括多个存储体，分配给各个存储体的多个读/写总线和分配给各个读/写总线并经由存储芯片布置的多个贯穿电极。 布置在层叠方向上看到的相同位置的穿透电极在芯片之间共同连接。 响应于访问请求，存储器芯片激活被布置在层叠方向上的各个不同位置的存储体，由此通过位于不同平面位置的穿透电极同时输入/输出数据。

    Semiconductor device including a delay locked loop circuit
    53.
    发明授权
    Semiconductor device including a delay locked loop circuit 有权
    半导体器件包括延迟锁定环电路

    公开(公告)号：US08917130B2

    公开(公告)日：2014-12-23

    申请号：US14152488

    申请日：2014-01-10

    申请人： Ryo Fujimaki

    发明人： Ryo Fujimaki

    IPC分类号： H03L7/00 ,  H03L7/10 ,  H03L7/081

    CPC分类号： H03L7/10 ,  H03L7/0814

    摘要： A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay elements as an output clock signal. The method includes resetting an initial delay control circuit, generating, with the initial delay control circuit, a pulse based on a period of an input clock signal, determining, with the initial delay control circuit, a number of delay elements required to produce a delay time at least substantially equivalent to a pulse width for a preset signal, initializing the counter circuit based on the preset signal and adjusting the counter circuit in response to phases of the input and output clock signals.

    摘要翻译： 用于初始化具有延迟电路的延迟锁定环路的方法包括多个串行连接的延迟元件和用于选择延迟元件之一的输出作为输出时钟信号的计数器电路。 该方法包括复位初始延迟控制电路，利用初始延迟控制电路产生基于输入时钟信号的周期的脉冲，利用初始延迟控制电路确定产生延迟所需的延迟元件的数量 时间至少基本上等于预设信号的脉冲宽度，基于预置信号初始化计数器电路，并响应于输入和输出时钟信号的相位调整计数器电路。

    Semiconductor device
    55.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08886893B2

    公开(公告)日：2014-11-11

    申请号：US12597097

    申请日：2008-04-25

    申请人： Seiji Miura ,  Yoshinori Haraguchi ,  Kazuhiko Abe ,  Shoji Kaneko

    发明人： Seiji Miura ,  Yoshinori Haraguchi ,  Kazuhiko Abe ,  Shoji Kaneko

    IPC分类号： G06F12/00 ,  G11C7/00 ,  G06F13/42

    CPC分类号： G11C14/00 ,  G06F13/4243 ,  G11C16/30

    摘要： The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.

    摘要翻译： 本发明的目的是提供一种高速，低成本和用户友好的信息处理系统，其可以确保存储器容量的可扩展性。 信息处理系统被配置为包括信息处理设备，易失性存储器和非易失性存储器。 通过串行连接信息处理装置，易失性存储器和非易失性存储器并减少连接信号的数量，提高处理速度，同时保持存储容量的可扩展性。 当将非易失性存储器的数据传送到易失性存储器时，执行错误校正，从而提高可靠性。 包括多个芯片的信息处理系统被配置为信息处理系统模块，其中芯片被交替堆叠和布置，并且由球栅阵列（BGA）或芯片之间的接合进行布线。

    Semiconductor device changing an active time-out time interval
    56.
    发明授权
    Semiconductor device changing an active time-out time interval 有权
    半导体器件改变主动超时时间间隔

    公开(公告)号：US08885431B2

    公开(公告)日：2014-11-11

    申请号：US13137030

    申请日：2011-07-15

    申请人： Tomoaki Sato

    发明人： Tomoaki Sato

    IPC分类号： G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622

    摘要： A device includes a plurality of memory areas each including a plurality of memory cells required to perform refresh of information stored therein by a plurality of sense amplifiers, a first control circuit determining, in connection with one refresh requirement signal at a time, a number of refresh-target memory areas to produce a determined number, a second control circuit controlling, in accordance with the one refresh requirement signal at a time, refresh operation with respect to the refresh-target memory areas, and a third control circuit adjusting, in connection with the refresh operation, an active time-out time interval according to the determined number. The active time-out time interval indicates a time interval from a first time instant when the sense amplifiers are activated to a second time instant when word lines related to the refresh-target memory areas are inactivated.

    摘要翻译： 一种设备包括多个存储区域，每个存储区域包括执行由多个读出放大器存储的信息的刷新所需的多个存储器单元;第一控制电路一次确定与一次刷新需求信号相关的数量 刷新目标存储器区域以产生确定的数量，第二控制电路根据一次刷新需求信号一次控制相对于刷新目标存储区域的刷新操作，以及第三控制电路，在连接中调整 随着刷新操作，根据确定的数量，有效的超时时间间隔。 激活超时时间间隔表示当从与刷新目标存储器区域相关的字线被激活时，将感测放大器激活的第一时刻到第二时刻的时间间隔。

    Semiconductor device having data output circuit in which slew rate thereof is adjustable
    58.
    发明授权
    Semiconductor device having data output circuit in which slew rate thereof is adjustable 有权
    具有其压摆率可调的数据输出电路的半导体装置

    公开(公告)号：US08872560B2

    公开(公告)日：2014-10-28

    申请号：US13710626

    申请日：2012-12-11

    申请人： Elpida Memory, Inc.

    发明人： Yoshihito Morishita ,  Tetsuya Arai

    IPC分类号： H03K5/12 ,  H03K3/00 ,  H03K19/003

    CPC分类号： H03K5/12 ,  H03K3/00 ,  H03K19/00361

    摘要： Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals.

    摘要翻译： 这里公开了一种装置，其包括：第一电路，被配置为在第一电源电压上操作以产生第一组转换速率控制信号; 第二电路，被配置为响应于所述第一组转换速率控制信号而在第二电源电压上操作以产生第二组转换速率控制信号; 以及第三电路，被配置为对所述第二电源电压进行操作，以响应于所述第二组压摆率控制信号可控制的速率产生信号。