公开(公告)号：US20180181315A1

公开(公告)日：2018-06-28

申请号：US15392857

申请日：2016-12-28

Applicant: Amazon Technologies, Inc.

Inventor： NORBERT P. KUSTERS ,  NACHIAPPAN ARUMUGAM ,  CHRISTOPHER NATHAN WATSON ,  MARC JOHN BROOKER ,  DAVID R. RICHARDSON ,  DANNY WEI ,  JOHN LUTHER GUTHRIE, II

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0685 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/222 ,  G06F2212/262 ,  G06F2212/286 ,  G06F2212/461 ,  G06F2212/466 ,  G06F2212/7208 ,  G11B33/128 ,  H03M13/154 ,  H04L67/1095 ,  H04L67/1097 ,  H04L67/2842 ,  H04L67/2885 ,  Y02D10/13

Abstract: A data storage system includes multiple head nodes and multiple data storage sleds mounted in a rack. For a particular volume or volume partition one of the head nodes is designated as a primary head node for the volume or volume partition. The primary head node is configured to store data for the volume in a data storage of the primary head node and cause the data to be replicated to a secondary head node. The primary head node is also configured to cause the data for the volume to be stored in a plurality of respective mass storage devices each in different ones of the plurality of data storage sleds of the data storage system.

公开(公告)号：US20180173629A1

公开(公告)日：2018-06-21

申请号：US15846297

申请日：2017-12-19

Applicant: EMC IP Holding Company LLC

Inventor： Xinlei Xu ,  Jian Gao ,  Yousheng Liu ,  Changyu Feng ,  Geng Han

IPC: G06F12/0855 ,  G06F12/0891

CPC classification number: G06F12/0855 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601

Abstract: A method and system for managing a buffer device in a storage system. The method comprising determining a first priority for a first queue included in the buffer device, the first queue comprising at least one data page associated with a first storage device in the storage system; in at least one round, in response to the first priority not satisfying a first predetermined condition, updating the first priority according to a first updating rule, the first updating rule making the updated first priority much closer to the first predetermined condition than the first priority; and in response to the first priority satisfying the first predetermined condition, flushing data in a data page in the first queue to the first storage device.

公开(公告)号：US10001927B1

公开(公告)日：2018-06-19

申请号：US14501455

申请日：2014-09-30

Applicant: EMC IP Holding Company LLC

Inventor： Michael Trachtman ,  Brian Lake

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0862 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/312 ,  G06F2212/6026

Abstract: Described are techniques for processing I/O operations. A read operation is received that is directed to a first location of a logical device. Data stored at the first location of the logical device is replicated on a plurality of data storage systems. In accordance with one or more criteria, a set of at least one of the plurality of data storage systems is determined. The one or more criteria include information describing current configuration options of the plurality of data storage systems affecting I/O operation performance. The read operation is sent to each data storage system of the set.

公开(公告)号：US10001921B2

公开(公告)日：2018-06-19

申请号：US14795917

申请日：2015-07-10

Applicant: FUJITSU LIMITED

Inventor： Atsushi Ninomiya

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0893 ,  G06F12/0868

CPC classification number: G06F12/0893 ,  G06F12/0868 ,  G06F2212/283

Abstract: A data migration method includes creating, by a first control processor that controls a first cache memory storing first cache data cached from first storage data stored in a storage, first management information including information indicating a storage location of the first cache data on the first cache memory and information indicating whether or not the first storage data has been updated in accordance with an update of the first cache data for each block of a predetermined data size in the first cache memory, when a program that accesses the first cache data migrates to a different node, transmitting, by the first control processor, the first management information to a second control processor that controls a second cache memory capable of being accessed by the program after migration to the different node.

公开(公告)号：US20180165198A1

公开(公告)日：2018-06-14

申请号：US15378508

申请日：2016-12-14

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu

IPC: G06F12/0815 ,  G06F12/0891

CPC classification number: G06F12/0815 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/466 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/7201 ,  G06F2212/7207

Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.

公开(公告)号：US09996487B2

公开(公告)日：2018-06-12

申请号：US14751899

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Jose S. Niell ,  Daniel F. Cutter ,  Stephen J. Robinson ,  Mukesh K. Patel

IPC: G06F13/36 ,  G06F11/00 ,  G06F13/28 ,  G06F13/40 ,  G06F12/0868

CPC classification number: G06F13/28 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0868 ,  G06F13/4068 ,  G06F2212/1032 ,  G06F2212/608

Abstract: An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.

公开(公告)号：US09996471B2

公开(公告)日：2018-06-12

申请号：US15194902

申请日：2016-06-28

Applicant: ARM Limited

Inventor： Ali Saidi ,  Kshitij Sudan ,  Andrew Joseph Rushing ,  Andreas Hansson ,  Michael Filippo

IPC: G06F12/0871 ,  G06F12/0873 ,  G06F12/0895

CPC classification number: G06F12/0871 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0895 ,  G06F2212/305 ,  G06F2212/401 ,  G06F2212/466

Abstract: Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.

公开(公告)号：US09990142B2

公开(公告)日：2018-06-05

申请号：US15256594

申请日：2016-09-04

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Shuwei Wu ,  Bin Feng ,  Bin Sai

IPC: G06F3/06 ,  G06F12/0868

CPC classification number: G06F3/0611 ,  G06F3/0643 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0673 ,  G06F12/0868

Abstract: A mass storage system for storing mass data generated by a mass data source. The system includes a data buffer coupled to the mass data source, and a file system and command generator. The data buffer caches the mass data. The file system and command generator generates file system data corresponding to the mass data stored in the data buffer. The file system and command generator also automatically configures a SATA host controller so that the SATA host controller will move the cached mass data and the generated file system data to a mass storage device.

公开(公告)号：US20180150404A1

公开(公告)日：2018-05-31

申请号：US15704943

申请日：2017-09-14

Applicant: DONG-GUN KIM ,  DAE-HO KIM ,  HONG-MOON WANG ,  WON-MOON CHEON

Inventor： DONG-GUN KIM ,  DAE-HO KIM ,  HONG-MOON WANG ,  WON-MOON CHEON

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F12/0868 ,  G06F2212/202 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7207

Abstract: An electronic system includes a host device and a storage device. The storage device includes a first memory device that is accessed by the host device by units of a byte through a byte accessible interface and a second memory device that is accessed by the host device by units of a block through a block accessible interface. The storage device performs an internal data transfer between the first memory device and the second memory device based on an internal transfer command that is provided through the block accessible interface from the host device. The electronic system may efficiently support the access by units of a byte and the access by units of a block between the host device and the storage device by performing internal data transfer in the storage device using the internal transfer command that is modified from the existing block access command.

公开(公告)号：US20180150309A1

公开(公告)日：2018-05-31

申请号：US15880092

申请日：2018-01-25

Applicant: Dynavisor, Inc.

Inventor： Sreekumar Nair

IPC: G06F9/455 ,  G06F12/0868 ,  G06F3/06 ,  G06F12/1081 ,  G06F13/28 ,  G06F9/4401 ,  G06F12/084 ,  G06F12/0864

CPC classification number: G06F9/45533 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0685 ,  G06F3/0689 ,  G06F9/4411 ,  G06F9/45558 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/1081 ,  G06F13/28 ,  G06F2003/0692 ,  G06F2009/45579 ,  G06F2212/152 ,  G06F2212/2532 ,  G06F2212/314 ,  G06F2212/463

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.