公开(公告)号：US20230395128A1

公开(公告)日：2023-12-07

申请号：US17830042

申请日：2022-06-01

申请人： Micron Technology, Inc.

发明人： Lorenzo Fratin ,  Fabio Pellizzer ,  Paolo Fantini

IPC分类号： G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/06

CPC分类号： G11C11/4087 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/063

摘要： Methods, systems, and devices for decoder architectures for three-dimensional memory devices are described. In some cases, a decoder for a memory device may include two portions. A first portion of the decoder may be manufactured on top of the memory array, and may include a pillar decoding portion to selectively bias a first array of decoding elements coupled with conductive pillars of the memory array and a word line decoding portion to selectively bias a second array of decoding elements coupled with word lines of the memory array. A second portion of the decoder may be implemented in a separate semiconductor device which may include a set of logic circuits configured to drive signal to a set of contacts bonded to contacts of the first portion to drive the digit lines, voltage sources, and gate lines.

公开(公告)号：US20230395113A1

公开(公告)日：2023-12-07

申请号：US18203877

申请日：2023-05-31

申请人： Micron Technology, Inc.

发明人： Giorgio Servalli ,  Marcello Mariani ,  Agostino Pirovano

IPC分类号： G11C11/22 ,  G11C5/06 ,  H10B53/10 ,  H10B53/20 ,  H01L29/51

CPC分类号： G11C11/2253 ,  G11C11/221 ,  H01L29/516 ,  H10B53/10 ,  H10B53/20 ,  G11C5/063

摘要： Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.

公开(公告)号：US20230395097A1

公开(公告)日：2023-12-07

申请号：US18231235

申请日：2023-08-07

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC分类号： G11C5/06 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  G11C16/04 ,  H10B41/35 ,  H01L29/49

CPC分类号： G11C5/063 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  G11C16/0483 ,  H10B41/35 ,  H01L29/495

摘要： A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where each of the at least one memory transistor is directly connected to at least one of the plurality of bit-line pillars, where the plurality of memory cells include a partially or fully metalized source structure and/or a partially or fully metalized drain structure, where the metalized source includes two metal structures, and where the two metal structures include a tungsten structure.

公开(公告)号：US11818878B2

公开(公告)日：2023-11-14

申请号：US17868722

申请日：2022-07-19

申请人： Zeno Semiconductor, Inc.

发明人： Benjamin S Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

IPC分类号： G11C5/06 ,  H10B12/00 ,  H01L21/265 ,  G11C16/04 ,  H01L27/088 ,  H01L29/66 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  H01L29/78 ,  H01L23/528 ,  G11C11/4096 ,  G11C11/4099 ,  H01L29/10

CPC分类号： H10B12/20 ,  G11C5/063 ,  G11C11/4096 ,  G11C11/4099 ,  G11C16/0416 ,  G11C16/0483 ,  H01L21/26586 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/785 ,  H01L29/7841 ,  H10B12/50 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  G11C2211/4016

摘要： NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

公开(公告)号：US11818876B2

公开(公告)日：2023-11-14

申请号：US17563286

申请日：2021-12-28

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tseng-Fu Lu

IPC分类号： H10B12/00 ,  G11C5/06

CPC分类号： H10B12/0335 ,  G11C5/063 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/488

摘要： The present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate comprising one or more isolation features defining active regions; forming at least one access transistor comprising a plurality of impurity regions, wherein the impurity regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated impurity region; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first and second contact holes.

公开(公告)号：US11804404B2

公开(公告)日：2023-10-31

申请号：US17450833

申请日：2021-10-14

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chao-Wen Lay

IPC分类号： H10B12/00 ,  H01L21/768 ,  G11C5/06 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L21/76837 ,  G11C5/063 ,  H01L21/76828 ,  H01L23/5283 ,  H01L23/5329 ,  H10B12/482

摘要： A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.

公开(公告)号：US11800718B2

公开(公告)日：2023-10-24

申请号：US17375498

申请日：2021-07-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Chih Lai ,  Chung-Te Lin

IPC分类号： H10B43/35 ,  G11C5/06 ,  H10B43/10 ,  H10B43/40

CPC分类号： H10B43/35 ,  G11C5/063 ,  H10B43/10 ,  H10B43/40

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a via above a substrate, a dielectric layer over the via, a first source/drain feature above the dielectric layer, a first channel feature above the first source/drain feature, a second source/drain feature above the first channel feature, and a gate line laterally spaced apart from the first source/drain feature, the first channel feature and the second source/drain feature. The gate line passes through the dielectric layer and is on the via.

公开(公告)号：US20230328960A1

公开(公告)日：2023-10-12

申请号：US17954117

申请日：2022-09-27

申请人： SK hynix Inc.

发明人： Eun Jeong KIM ,  Ji Hoon Kim ,  Hun Joo Lee

IPC分类号： H01L27/108 ,  G11C5/06

CPC分类号： H01L27/10814 ,  G11C5/063 ,  H01L27/10897

摘要： A semiconductor device includes a substrate having a cell area and a peripheral area, transistors in the peripheral area over the substrate, a lower interlayer insulating layer between the transistors, interconnections and a first spacer layer over the transistors and the lower interlayer insulating layer, an upper interlayer insulating layer over the interconnections and the first spacer layer. The first spacer layer is disposed between the interconnections, The first spacer layer includes a first lower spacer layer and a first upper spacer layer over the first lower spacer layer. The first lower spacer layer and the first upper spacer layer include silicon, boron, and nitrogen. A boron concentration of the first lower spacer layer is different from a boron concentration of the first upper spacer layer.

公开(公告)号：US11785710B2

公开(公告)日：2023-10-10

申请号：US17947397

申请日：2022-09-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Wonseop Lee ,  Hwanwook Park ,  Jeonghoon Baek ,  Dohyung Kim ,  Seunghee Mun ,  Dongyoon Seo ,  Jinoh Ahn

IPC分类号： G11C5/04 ,  H05K1/02 ,  H01L25/11 ,  H01L25/065 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40

CPC分类号： H05K1/0246 ,  G06F13/4086 ,  G11C5/04 ,  G11C5/063 ,  G11C8/18 ,  H01L25/0657 ,  H01L25/112 ,  H05K1/025 ,  H05K2201/10159

摘要： A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

公开(公告)号：US20230317121A1

公开(公告)日：2023-10-05

申请号：US17709174

申请日：2022-03-30

申请人： MACRONIX International Co., Ltd.

发明人： Chung-Kuang Chen ,  Tzeng-Huei Shiau

IPC分类号： G11C5/14 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C5/063 ,  H01L23/5223 ,  H01L23/528

摘要： A capacitor string structure, a memory device and a charge pump circuit thereof are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.