公开(公告)号：US12142566B2

公开(公告)日：2024-11-12

申请号：US18206539

申请日：2023-06-06

Applicant: Intel Corporation

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20240373628A1

公开(公告)日：2024-11-07

申请号：US18774012

申请日：2024-07-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Tuo Huang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H10B41/30 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

公开(公告)号：US20240373614A1

公开(公告)日：2024-11-07

申请号：US18771937

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H10B10/00 ,  G11C11/412 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US20240371973A1

公开(公告)日：2024-11-07

申请号：US18773070

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon Lim ,  Cheng-Lung Hung ,  Mao-Lin Huang ,  Weng Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

公开(公告)号：US20240371644A1

公开(公告)日：2024-11-07

申请号：US18778304

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

公开(公告)号：US12136659B2

公开(公告)日：2024-11-05

申请号：US18362064

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L21/266 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US20240363352A1

公开(公告)日：2024-10-31

申请号：US18767601

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chandrashekhar Prakash SAVANT ,  Tien-Wei YU ,  Chia-Ming TSAI

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.

公开(公告)号：US20240357831A1

公开(公告)日：2024-10-24

申请号：US18532504

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seryeun Yang ,  Jeon Il Lee ,  Hyeran Lee ,  Hyun-Mook Choi

IPC: H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

CPC classification number: H10B53/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A semiconductor device may include a substrate; semiconductor patterns that are stacked on the substrate, extend in a first direction parallel to a top surface of the substrate, and are spaced apart from each other; a gate electrode including horizontal portions, that extend in a second direction crossing the first direction, and a vertical portion, that is in contact with the horizontal portions and extends in a third direction perpendicular to the top surface of the substrate; a gate dielectric layer between the semiconductor patterns and the gate electrode; and a ferroelectric layer between the gate dielectric layer and the gate electrode. Each of the semiconductor patterns may include impurity regions and a channel region between the impurity regions, the vertical portion may be on a first side surface of the channel region, and the horizontal portions may be on a top and bottom surface of the channel region.

公开(公告)号：US20240355903A1

公开(公告)日：2024-10-24

申请号：US18763777

申请日：2024-07-03

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Dax M. CRUM ,  Stephen M. CEA ,  Leonard P. GULER ,  Tahir GHANI

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6653 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7853

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

公开(公告)号：US20240355668A1

公开(公告)日：2024-10-24

申请号：US18637949

申请日：2024-04-17

Applicant: CANON MEDICAL SYSTEMS CORPORATION

Inventor： Tatsuya SUZUKI ,  Nobuhiko SATO

IPC: H01L21/70 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/707 ,  H01L21/0214 ,  H01L21/0228 ,  H01L21/28202 ,  H01L21/823475

Abstract: A semiconductor apparatus according to an embodiment of the present disclosure includes: a substrate; a wiring layer serving as a topmost layer formed over the substrate; a first protection film formed so as to cover the wiring layer; a planarization film formed on the first protection film; and a second protection film formed on the planarization film. The first protection film and the second protection film are each thicker than the planarization film.