公开(公告)号：US09431129B2

公开(公告)日：2016-08-30

申请号：US14266326

申请日：2014-04-30

申请人： QUALCOMM Incorporated

发明人： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Xiangyu Dong

IPC分类号： G11C29/02 ,  G11C29/30 ,  G11C7/10 ,  G11C16/26 ,  G11C16/30 ,  G11C14/00 ,  G06F11/10 ,  G11C29/52 ,  G11C7/06 ,  G11C7/08 ,  G11C29/04 ,  G11C11/16 ,  G11C13/00

CPC分类号： G11C29/026 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/16 ,  G11C11/1673 ,  G11C13/004 ,  G11C14/0081 ,  G11C14/009 ,  G11C16/26 ,  G11C16/30 ,  G11C29/30 ,  G11C29/52 ,  G11C2029/0411

摘要： A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.

摘要翻译： 一种器件包括存储器阵列的多个存储单元，存储器阵列的读出放大器和存储器阵列的选择逻辑。 感测放大器被配置为感测来自多个存储器单元中的至少一个存储单元的至少一个数据值。 选择逻辑被配置为在使感测放大器使用第一感测延迟来感测至少一个数据值并且使得感测放大器使用第二感测延迟来感测至少一个数据值之间进行选择。 第二感测延迟比第一感测延迟更长。

公开(公告)号：US20150143188A1

公开(公告)日：2015-05-21

申请号：US14326731

申请日：2014-07-09

申请人： Silicon Motion, Inc.

发明人： Han-Cheng HUANG

IPC分类号： G06F11/10 ,  G11C29/24 ,  G11C29/30

CPC分类号： G11C29/24 ,  G06F11/1008 ,  G11C16/00 ,  G11C29/08 ,  G11C29/30 ,  G11C29/82 ,  G11C2029/1204 ,  G11C2029/4402

摘要： An embodiment of a method for accessing a storage unit of a flash memory, performed by a control unit, is disclosed to include at least the following steps. A transaction is appended to a bad-column table each time a bad column of a block within the storage unit is inspected. It is determined whether a total number of the transactions within the bad-column table is odd when the control unit determines that the last column of the block is a regular column. A transaction is appended to the bad-column table to indicate that the last column of the block is a bad column when the control unit determines that the total number of the transactions within the bad-column table is odd.

摘要翻译： 公开了一种用于访问由控制单元执行的闪速存储器的存储单元的方法的实施例，至少包括以下步骤。 每次检查存储单元中块的坏列时，事务将附加到坏列表。 当控制单元确定块的最后一列是常规列时，确定坏列表中的事务的总数是否为奇数。 当控制单元确定坏列表中的事务总数为奇数时，事务将附加到坏列表，以指示块的最后一列是错误列。

公开(公告)号：US07305594B2

公开(公告)日：2007-12-04

申请号：US10303179

申请日：2002-11-25

申请人： James J. Dietz ,  David SuitWai Ma

发明人： James J. Dietz ,  David SuitWai Ma

IPC分类号： G11C29/30 ,  G11C29/40

CPC分类号： G11C29/1201 ,  G11C29/48

摘要： A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a greatest number of input/output paths. In the operating architecture, the memory enables the same or fewer input/output paths. The method of selecting a configuration includes establishing an operating and a test architecture and testing the memory in its greater input/output configuration.

摘要翻译： 存储器包括输入/​​输出路径和电引线。 每个输入/输出路径被耦合到单独的电引线。 存储器被配置为在测试架构和操作架构中操作。 在测试架构中，逻辑允许最大数量的输入/输出路径。 在操作架构中，内存使能相同或更少的输入/输出路径。 选择配置的方法包括建立操作和测试体系结构，并以更大的输入/输出配置测试存储器。

公开(公告)号：US07210084B2

公开(公告)日：2007-04-24

申请号：US10413612

申请日：2003-04-14

申请人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald Plass

IPC分类号： G11C29/30 ,  G11C29/24

CPC分类号： G11C29/40 ,  G11C11/41

摘要： ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.

摘要翻译： 具有集成目录比较逻辑功能的ABIST设备和ABIST错误检测功能。 该装置包括NORs在一起的两个子系统。 第一个子系统用于逐位逻辑地对应阵列有效位和标签有效输入，为匹配产生“0”，为了匹配而产生“1”，逻辑上对位逐次结果产生“1” 如果有任何比特错配，则打。 第二子系统进一步接收ABIST控制逻辑作为输入：（a）。 组合数组有效位​​标签有效输入以产生有效输出，或（b）将数组有效位​​与标签有效输入进行比较。 该装置还包括用于第一和第二子系统的输出的逻辑NOR功能。

公开(公告)号：US07145818B2

公开(公告)日：2006-12-05

申请号：US10806417

申请日：2004-03-23

申请人： Tetsuya Fukuoka ,  Mikio Yamagishi

发明人： Tetsuya Fukuoka ,  Mikio Yamagishi

IPC分类号： G11C29/30

CPC分类号： G11C29/1201 ,  G01R31/318536 ,  G11C29/46 ,  G11C2029/3202

摘要： A semiconductor integrated circuit device is provided with a diagnosis circuit, which does not increase the delay of a logic element in normal operation. In a latch provided at the output of a memory or at the input of a logic stage, a signal selector is provided in the feedback loop of the latch. The selector is switched in correspondence with the operation mode, such that it transfers the feedback signal in normal operation, while it transfers the test signal in a test mode, in order to prevent the delay from increasing in the signal selector on the main path in normal operation.

摘要翻译： 半导体集成电路器件设置有诊断电路，其不会在正常操作中增加逻辑元件的延迟。 在设置在存储器的输出处或在逻辑级的输入处的锁存器中，在锁存器的反馈回路中提供信号选择器。 选择器与操作模式相对应地切换，使得它在正常操作中传送反馈信号，同时在测试模式下传送测试信号，以防止在主路径上的信号选择器中的延迟增加 普通手术。

公开(公告)号：US6160276A

公开(公告)日：2000-12-12

申请号：US344220

申请日：1999-06-25

申请人： Amr M. Mohsen

发明人： Amr M. Mohsen

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/30 ,  H01L21/66 ,  H01L23/525 ,  H01L23/528 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H01L27/10

CPC分类号： H01L22/22 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318505 ,  G01R31/318538 ,  G11C29/30 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0286 ,  H01L2924/00

摘要： An interconnect structure is centered around a substrate having opposite first and second surfaces. Component contacts allocated to cells in the substrate, are provided over both substrate surfaces. Conductive leads extend over each surface in two different directions. The conductive leads are selectively connected to the component contacts. The interconnect structure includes a capability for programmability electrically connecting, or disconnecting, the conductive leads in a desired manner.

摘要翻译： 互连结构围绕具有相反的第一和第二表面的衬底居中。 分配给基板中的单元的组件触点设置在两个基板表面上。 导电引线在两个不同方向上在每个表面上延伸。 导电引线选择性地连接到元件触点。 互连结构包括以可期望的方式电连接或断开导电引线的可编程性能。

公开(公告)号：US5504354A

公开(公告)日：1996-04-02

申请号：US300289

申请日：1994-09-02

申请人： Amr M. Mohsen

发明人： Amr M. Mohsen

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/30 ,  H01L21/66 ,  H01L23/525 ,  H01L23/528 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H01L27/10 ,  H01L23/48

CPC分类号： H01L22/22 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318505 ,  G01R31/318538 ,  G11C29/30 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0286

摘要： An interconnect structure contains an interconnect substrate, multiple component contacts formed on the interconnect substrate for receipt of electronic components, and multiple conductive traces formed on the interconnect substrate. Each conductive trace is electrically connected to one of the component contacts. An IC having a group of parallel of conductive leads is mounted on the substrate. At least one of the conductive leads is divided into two or more segments. One or more of the conductive leads or segments are connected to corresponding conductive traces on the interconnect substrate. In one embodiment, the IC is a programmable chip having programmable elements for selectively connecting the conductive leads or segments, thereby enabling a user to interconnect selected conductive traces on the interconnect substrate to achieve a desired electrical function from the electronic components connected to the substrate. In another embodiment, the IC contains active devices for testing the IC's conductive leads, the conductive traces on the substrate, and/or the electronic components mounted on the component contacts.

摘要翻译： 互连结构包括互连衬底，形成在互连衬底上的用于接收电子部件的多个部件触点以及形成在互连衬底上的多个导电迹线。 每个导电迹线电连接到组件触点中的一个。 具有一组导电引线平行的IC安装在基板上。 至少一个导电引线被分成两个或更多个段。 一个或多个导电引线或段连接到互连衬底上的对应导电迹线。 在一个实施例中，IC是具有用于选择性地连接导电引线或段的可编程元件的可编程芯片，从而使用户能够互连互连衬底上的选定的导电迹线，以从连接到衬底的电子部件获得期望的电功能。 在另一个实施例中，IC包含用于测试IC导电引线，衬底上的导电迹线和/或安装在元件触点上的电子元件的有源器件。

公开(公告)号：US5371390A

公开(公告)日：1994-12-06

申请号：US972884

申请日：1992-11-04

申请人： Amr M. Mohsen

发明人： Amr M. Mohsen

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/30 ,  H01L21/66 ,  H01L23/525 ,  H01L23/528 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H01L23/52

CPC分类号： H01L22/22 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318505 ,  G01R31/318538 ,  G11C29/30 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0286

摘要： An interconnect structure contains a substrate, a layer of separate conductive leads extending over the substrate in one direction, and another layer of separate conductive leads extending over the substrate in another, substantially different, direction. At least one conductive lead in each of the layers of conductive leads is divided into at least two electrically separate conductive segments. A plurality of cells are formed in the substrate. Each cell has a number of bonding pads formed above the substrate region where the cell is situated for allowing integrated circuit chips and/or electronic components to be connected to the cells. Programmable elements, typically programmed by devices in the substrate, enable connections to be formed between selected ones of the conductive leads or segments, thus enabling the integrated circuit chips and electronic components to be electrically interconnected. Devices formed in the substrate typically allow testing of the various components connected to the substrate to determine their performance and to check the integrity of the connections formed between the conductive leads or segments.

摘要翻译： 互连结构包含衬底，在一个方向上在衬底上延伸的单独的导电引线层，以及在另一个基本不同的方向上在衬底上延伸的另一层分开的导电引线。 每个导电引线层中的至少一个导电引线被分成至少两个电分离的导电段。 在基板中形成多个单元。 每个单元具有形成在单元所在的基板区域上方的多个接合焊盘，用于允许集成电路芯片和/或电子部件连接到单元。 通常由衬底中的器件编程的可编程元件使得能够在导电引线或段之间的选定导体之间形成连接，从而使集成电路芯片和电子部件能够电互连。 在衬底中形成的器件通常允许测试连接到衬底的各种部件以确定其性能并且检查在导电引线或段之间形成的连接的完整性。

公开(公告)号：US5184327A

公开(公告)日：1993-02-02

申请号：US727218

申请日：1991-07-09

申请人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C29/30

CPC分类号： G11C29/30

摘要： In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15 20). The output line (L) is provided with plural junction points (n1 to nn) to which detection results from the detection circuits (14, 15 20) are separately applied. Dividing transistors (T1 to Tn) are provided between the junction points (n1 to nn). During testing, the word lines (WL1 to WLn) are selected sequentially. Test results for the memory cells (MC1 to MC4) connected to the selected word line are outputted at the corresponding junction points (n1 to nn), respectively. Simultaneously, a dividing transistor corresponding to the selected word line is rendered non-conductive, the remaining dividing transistors being rendered conductive. As a result, the output line (L) is divided into two parts at a portion of the non-conductive transistor. Detection results outputted to the respective divided parts of the output line (L) are monitored and a portion at which a detection result is changed in each divided part is found out.

摘要翻译： 在半导体存储器件的存储单元阵列中，与多个列对应地提供多个检测电路（14,15,20）。 输出线（L）与检测电路（14,1520）共同设置。 输出线（L）具有分别施加有检测电路（14,15,20）的检测结果的多个连接点（n1〜nn）。 分接晶体管（T1至Tn）设置在连接点（n1至nn）之间。 在测试期间，顺序选择字线（WL1至WLn）。 连接到所选字线的存储单元（MC1至MC4）的测试结果分别在对应的连接点（n1至nn）输出。 同时，与所选字线对应的分割晶体管不导通，剩余的分割晶体管导通。 结果，输出线（L）在非导电晶体管的一部分被分成两部分。 检测输出到输出线（L）的分割部分的检测结果，并且求出检测结果在各分割部分发生变化的部分。

公开(公告)号：US5099481A

公开(公告)日：1992-03-24

申请号：US317001

申请日：1989-02-28

申请人： Michael J. Miller

发明人： Michael J. Miller

IPC分类号： G06F11/25 ,  G06F11/34 ,  G11C29/20 ,  G11C29/30

CPC分类号： G06F11/348 ,  G11C29/20 ,  G11C29/30 ,  G06F11/25

摘要： A serial protocol register and an initialization counter are configured to initialize (program) a RAM array. The register is configured to receive, in serial format, an initial address to be loaded into the counter. Also, the register is configured to receive, in serial format, a series of machine states (data words), each to be stored in the RAM array. In addition, the register is configured to clock the counter following each received machine state. The counter is configured to develop a series of addresses, each for accessing the RAM array to store in the array a corresponding one of the machine states.

摘要翻译： 串行协议寄存器和初始化计数器被配置为初始化（编程）RAM阵列。 寄存器被配置为以串行格式接收要加载到计数器中的初始地址。 此外，寄存器被配置为以串行格式接收一系列机器状态（数据字），每个机器状态存储在RAM阵列中。 此外，寄存器配置为在每个接收的机器状态之后对计数器进行计时。 计数器被配置为开发一系列地址，每个地址用于访问RAM阵列以在阵列中存储对应的一个机器状态。