公开(公告)号：US10447270B2

公开(公告)日：2019-10-15

申请号：US16148977

申请日：2018-10-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03K19/0185 ,  H03K19/0944 ,  H03K19/20

Abstract: A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.

公开(公告)号：US20190305925A1

公开(公告)日：2019-10-03

申请号：US16378084

申请日：2019-04-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L25/12 ,  H04L25/02 ,  H04L7/10

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US10431290B2

公开(公告)日：2019-10-01

申请号：US16139636

申请日：2018-09-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C8/00 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US10402352B2

公开(公告)日：2019-09-03

申请号：US15333001

申请日：2016-10-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/00 ,  G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G06F13/40 ,  G11C29/02

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US10402110B2

公开(公告)日：2019-09-03

申请号：US15642860

申请日：2017-07-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US10388355B1

公开(公告)日：2019-08-20

申请号：US15987884

申请日：2018-05-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G11C11/402 ,  G11C5/06 ,  G11C11/409

Abstract: A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.

公开(公告)号：US10388337B2

公开(公告)日：2019-08-20

申请号：US15889191

申请日：2018-02-05

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20190220399A1

公开(公告)日：2019-07-18

申请号：US16245749

申请日：2019-01-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

公开(公告)号：US20190205268A1

公开(公告)日：2019-07-04

申请号：US16223031

申请日：2018-12-17

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware

IPC: G06F13/16 ,  G11C7/10 ,  G06F12/1081 ,  G06F13/28 ,  G11C5/04 ,  G06F13/42 ,  H05K1/18

CPC classification number: G06F13/1642 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/4243 ,  G06F2212/656 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1075 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P70/611

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

公开(公告)号：US20190205222A1

公开(公告)日：2019-07-04

申请号：US16254920

申请日：2019-01-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G06F3/06 ,  G11C14/00 ,  G11C7/20

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0685 ,  G06F2201/805 ,  G06F2201/84 ,  G11C7/20 ,  G11C14/0018

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.