公开(公告)号：US09174445B1

公开(公告)日：2015-11-03

申请号：US14310633

申请日：2014-06-20

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Daniele Prati ,  Domenico Giusti ,  Simon Dodd

IPC: B41J2/05 ,  B41J2/14 ,  B41J2/16

CPC classification number: B41J2/14072 ,  B41J2/1404 ,  B41J2002/14362 ,  B41J2002/14403 ,  Y10T29/49352

Abstract: The present disclosure is directed to a microfluidic die having a substrate with an inlet path that is configured to move fluid into the die. The die includes a plurality of heaters formed above the substrate, each heater having a first area, a plurality of chambers formed above the plurality of heaters, and a plurality of nozzles formed above the chambers. Each nozzle having an entrance adjacent to the chamber and an exit adjacent to en external environment, the entrance having a second area, and the second having a third area, the first area being greater than the second area, and the second area being greater than the third area. A ratio of the first area to the third area being greater than 5 to 1.

Abstract translation: 本公开针对具有基底的微流体模具，该基底具有入口路径，该入口路径被配置为将流体移动到模具中。 模具包括形成在基板上方的多个加热器，每个加热器具有第一区域，形成在多个加热器上方的多个室以及形成在室上方的多个喷嘴。 每个喷嘴具有邻近室的入口和与外部环境相邻的出口，入口具有第二区域，第二区域具有第三区域，第一区域大于第二区域，第二区域大于第二区域 第三区。 第一区域与第三区域的比例大于5比1。

公开(公告)号：US20150311113A1

公开(公告)日：2015-10-29

申请号：US14264803

申请日：2014-04-29

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John Hongguang Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L23/5228 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask.

Abstract translation: 集成电路包括具有位于衬底上方的层间电介质层的衬底。 具有第一深度的第一沟槽形成在层间电介质层中，并且金属材料填充第一沟槽以形成第一互连线。 具有第二深度的第二沟槽也形成在层间电介质层中并且填充有金属材料以形成第二互连线。 第一和第二互连线具有基本相等的间距，其优选实施方式是亚光刻间距，以及由于沟槽深度的不同导致的不同的电阻率。 第一和第二沟槽通过具有不同深度的对应的第一和第二开口的硬掩模的蚀刻工艺形成。 侧壁图像转印过程用于限定用于在硬掩模中形成第一和第二开口的亚光刻结构。

公开(公告)号：US20150303903A1

公开(公告)日：2015-10-22

申请号：US14255400

申请日：2014-04-17

Applicant: STMICROELECTRONICS, INC.

Inventor： Felix Kim ,  Mark A. Lysinger ,  Scott V. Ho

IPC: H03K5/003

CPC classification number: H03K5/003 ,  H03F1/30 ,  H03F2200/375 ,  H03G1/0088 ,  H03G3/30

Abstract: Gain offset and voltage offset compensation for a controllable gain element of a circuit is effected in response to a gain offset value and voltage offset value. A current operating condition of the circuit is sensed and compared to a nominal operating condition. If the current operating condition is outside the nominal operating condition by more than a threshold, a calibration operation to set the gain and voltage offset values is performed. The gain offset value is selected as a function of the sensed current operating condition. With respect to the voltage offset, differential input terminals of the controllable gain element are shunted and the output is measured. The measured output value of the controllable gain element is applied as the voltage offset value. The operating conditions at issue may be one or more of supply voltage and temperature.

Abstract translation: 响应于增益偏移值和电压偏移值来实现电路的可控增益元件的增益偏移和电压偏移补偿。 检测电路的当前工作状态并将其与标称工作条件进行比较。 如果当前工作条件超出标称工作状态超过阈值，则执行设置增益和电压偏移值的校准操作。 选择增益偏移值作为感测到的当前操作条件的函数。 关于电压偏移，可控增益元件的差分输入端子被分流并且测量输出。 可控增益元件的测量输出值被应用为电压偏移值。 所讨论的操作条件可以是电源电压和温度中的一个或多个。

公开(公告)号：US20150303282A1

公开(公告)日：2015-10-22

申请号：US14788737

申请日：2015-06-30

Applicant: STMICROELECTRONICS, INC.

Inventor： PIERRE MORIN ,  NICOLAS LOUBET

IPC: H01L29/66

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract translation: 描述形成应变通道鳍状FET的方法和结构。 可以使用在体基板上生长的不同晶格常数的两个外延层来形成finFET的鳍结构。 可以切割第一薄的应变外延层以形成用于翅片的应变消除的基础结构。 基础结构可以被约束在应变消除状态。 翅片结构可以在基底结构上的第二层中外延生长。 受限的碱基结构可以在外延生长的翅片中形成比在非约束基础结构中发生的更大量的应变。

公开(公告)号：US20150303218A1

公开(公告)日：2015-10-22

申请号：US14253904

申请日：2014-04-16

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Sylvain Maitrejean ,  Romain Wacquez

IPC: H01L27/12 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L21/266 ,  H01L21/306 ,  H01L21/84

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Abstract translation: 描述了在衬底上的半导体层中形成局部的，不同应变的区域的方法和结构。 可以对原始半导体层中的初始的，无约束的绝缘体上半导体衬底进行处理以形成不同应变的区域。 不同应变区域可能具有相反类型的应变。 不同区域中的菌株可以独立形成。

公开(公告)号：US09165867B1

公开(公告)日：2015-10-20

申请号：US14449492

申请日：2014-08-01

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia Cadag ,  Jefferson Talledo

IPC: H01L23/495 ,  H01L23/28 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L21/4832 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/49513 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device may include an integrated circuit (IC), and lead frame contact areas adjacent the IC. Each lead frame contact area may have an opening therein. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may also include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires. Solder balls are within the respective opening.

Abstract translation: 半导体器件可以包括集成电路（IC）和与IC相邻的引线框接触区域。 每个引线框架接触区域可以在其中具有开口。 半导体器件可以包括接合线，每个接合线将相应的引线框架接触区域与IC耦合。 半导体器件还可以包括围绕IC的封装材料，引线框架接触区域和接合线。 焊球在相应的开口内。

公开(公告)号：US09165853B2

公开(公告)日：2015-10-20

申请号：US14586231

申请日：2014-12-30

Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD ,  STMICROELECTRONICS, INC.

Inventor： Fuchao Wang ,  Olivier Leneel ,  Ravi Shankar

IPC: H05B1/02 ,  H01L23/34 ,  H05B3/12 ,  H05B3/34 ,  H05B3/02

CPC classification number: H05B3/0014 ,  H01L23/34 ,  H01L23/345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H05B1/0227 ,  H05B3/02 ,  H05B3/06 ,  H05B3/12 ,  H05B3/34 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

Abstract translation: 提供具有有源电路的集成电路。 加热元件邻近有源电路并且被配置为加热有源电路。 温度传感器也与有源电路相邻并且被配置为测量有源电路的温度。 温度控制器耦合到有源电路并被配置为从温度传感器接收温度信号。 温度控制器操作加热元件以加热有源电路以将有源电路的温度保持在所选择的温度范围内。

公开(公告)号：US20150279780A1

公开(公告)日：2015-10-01

申请号：US14314945

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen SPOONER ,  Nicole A. SAULNIER

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract translation: 公开了一种容纳小金属线和扩大直径通孔的波浪线互连结构。 扩大的直径通孔可以使用自对准双镶嵌工艺形成，而不需要单独的通孔光刻掩模。 扩大的直径通孔与下面的金属线的至少三侧直接接触，并且可以相对于金属线不对称地对准，以增加金属图案的堆积密度。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 具有扩大的直径通孔的互连结构也可以具有气隙，以减少电介质击穿的机会。 通过允许通孔占地面积超过金属线宽度的最小尺寸，可以为进一步的工艺世代清除路径，以继续将金属线收缩到低于10nm的尺寸。

公开(公告)号：US20150271021A1

公开(公告)日：2015-09-24

申请号：US14672977

申请日：2015-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  Aidan Cully ,  James D. Allen

IPC: H04L12/24 ,  H04L12/801 ,  H04L12/26

CPC classification number: H04L41/0833 ,  H04L12/2816 ,  H04L43/08 ,  H04L47/13 ,  H04W40/10 ,  Y02D30/20 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/23 ,  Y02D70/326

Abstract: In accordance with an embodiment, a network device includes a network controller and at least one network interface coupled to the network controller that includes at least one media access control (MAC) device configured to be coupled to at least one physical layer interface (PHY). The network controller may be configured to determine a network path comprising the at least one network interface that has a lowest power consumption and minimum security attributes of available media types coupled to the at least one PHY.

公开(公告)号：US09136869B2

公开(公告)日：2015-09-15

申请号：US14054586

申请日：2013-10-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Hakan C. Ozdemir ,  Razmik Karabed ,  Richard Barndt ,  Kuhong Jeong

IPC: H03M7/46 ,  G11B20/14 ,  H03M5/14 ,  G11B5/09

CPC classification number: H03M7/46 ,  G11B5/09 ,  G11B20/1403 ,  H03M5/145

Abstract: A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.

Abstract translation: 一种用游程长度有限的高速逆序编码模式来编码比特流的系统和方法。 根据一个实施例，RLL编码块包括具有预编码器的接收机，该预编码器可用于接收具有长度为M比特符号的N比特流，可用于识别不存在于M比特内的M比特的索引符号的直方图 接收的N位流。 可以将该索引符号用作编码符号块的关键，以便在RLL解码时确保唯一的可解码性。 最后，编码器可操作以对存储在流中的下一个符号执行对每个符号的异或运算。 这样的编码系统仅将一个长度为M位的符号添加到N位块，并且仍然产生足以支持高速率要求和严格的定时环控制的位流。