公开(公告)号：US5173439A

公开(公告)日：1992-12-22

申请号：US679568

申请日：1991-04-02

申请人： Somanath Dash ,  Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Brian J. Machesney ,  Nitin B. Parekh

发明人： Somanath Dash ,  Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Brian J. Machesney ,  Nitin B. Parekh

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/762

CPC分类号： H01L21/02063 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/76229

摘要： A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrate. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.4, to provide a planarized upper surface of SiO.sub.2 and Si.sub.3 N.sub.4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.

摘要翻译： 提供了一种在半导体衬底中形成平坦化介质填充的宽浅沟槽的方法。 将诸如Si 3 N 4的蚀刻停止层沉积到半导体衬底上，并且通过常规RIE通过Si 3 N 4形成宽的沟槽进入衬底。 包括沟槽的衬底的表面在其上形成符合衬底表面的SiO 2涂层。 将诸如多晶硅的耐蚀刻材料层沉积到SiO 2材料上。 然后通过化学机械抛光去除沟槽宽度外的多晶硅，以在下面暴露出SiO 2，同时在覆盖有多晶硅的沟槽上留下SiO 2。 然后将暴露的SiO 2 RIE蚀刻到Si 3 N 4上，在每个沟槽上留下带有耐蚀刻多晶硅的SiO 2塞。 然后通过机械抛光除去Si 3 N 4，从而在衬底的顶部提供SiO 2和Si 3 N 4的平坦化上表面。 本发明还可用于在具有填充有导电材料的沟槽的衬底上形成平坦化表面。

公开(公告)号：US4799990A

公开(公告)日：1989-01-24

申请号：US44374

申请日：1987-04-30

申请人： Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Paul C. Parries ,  Francis R. White

发明人： Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Paul C. Parries ,  Francis R. White

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/308

CPC分类号： H01L21/0337 ,  H01L21/76224

摘要： A method for self-aligning an isolation structure to a diffusion region. A first masking layer is formed on a semiconductor substrate, the first masking layer having at least one aperture sidewall which is substantially perpendicular to the semiconductor substrate. Dopant ions are implanted into the semiconductor substrate through the first masking layer to form a doped region. Sidewall spacers are then defined on the sidewalls of the aperture, and a sidewall image reversal process is carried out such that the sidewall spacers define trench apertures in a masking structure. Finally, isolation trenches are etched into the semiconductor substrate through the masking structure. Alternatively, the implantation step is carried out after the sidewall spacers are defined on the first masking layer.

公开(公告)号：US08877615B2

公开(公告)日：2014-11-04

申请号：US13431770

申请日：2012-03-27

申请人： Veeraraghavan S. Basker ,  David V. Horak ,  Hemanth Jagannathan ,  Charles W. Koburger, III

发明人： Veeraraghavan S. Basker ,  David V. Horak ,  Hemanth Jagannathan ,  Charles W. Koburger, III

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7845

摘要： A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.

摘要翻译： FinFET结构及其制造方法具有降低的Ceff和增强的应力。 finFET结构包括多个finFET结构和形成栅极堆叠的一部分的应力材料，并且在多个finFET结构中的相邻空间之间的空间中。

公开(公告)号：US08835305B2

公开(公告)日：2014-09-16

申请号：US13562953

申请日：2012-07-31

申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

IPC分类号： H01L21/4763 ,  H01L23/12 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.

摘要翻译： 可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。 在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

公开(公告)号：US08765585B2

公开(公告)日：2014-07-01

申请号：US13095955

申请日：2011-04-28

申请人： Su C. Fan ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Su C. Fan ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/311 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41775 ,  H01L29/66545

摘要： Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.

摘要翻译： 形成在衬底上的每个栅极结构包括栅极电介质，栅极导体，第一蚀刻停止层和栅极盖电介质。 在栅极结构，栅极间隔物以及源极和漏极区域上形成第二蚀刻停止层。 在第二蚀刻停止层上方形成第一接触电介质层和第二接触电介质层。 形成至少延伸到栅极盖电介质的顶表面的栅极接触通孔。 随后形成延伸到第一和第二接触电介质层之间的界面的源极/漏极接触孔。 通过同时蚀刻暴露的栅极帽电介质和第一接触电介质层的暴露部分，然后同时蚀刻第一和第二蚀刻停止层，使各种接触通孔垂直延伸。 从而形成与外表面自对准的源极/漏极接触孔。

公开(公告)号：US20130307086A1

公开(公告)日：2013-11-21

申请号：US13471852

申请日：2012-05-15

申请人： Charles W. Koburger, III ,  Marc A. Bergendahl ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Charles W. Koburger, III ,  Marc A. Bergendahl ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L27/088 ,  H01L21/283

CPC分类号： H01L29/401 ,  E21B43/305 ,  E21B47/122 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211

摘要： In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

摘要翻译： 在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。 介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。 使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。 将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。

公开(公告)号：US08568604B2

公开(公告)日：2013-10-29

申请号：US12186075

申请日：2008-08-05

申请人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： B44C1/22 ,  H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/823828 ,  H01L21/823864

摘要： A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

摘要翻译： 用于形成亚光刻结构的侧壁图像转印工艺采用沉积在结构层上并被覆盖层覆盖的牺牲材料层。 牺牲材料层和覆盖层用常规抗蚀剂图案化并蚀刻以形成牺牲芯棒。 心轴的边缘在低温下在等离子体中被氧化或氮化，之后剥离材料层和覆盖层，留下亚光刻的侧壁。 侧壁用作硬掩模来蚀刻栅极导体层中的亚光刻栅极结构。

公开(公告)号：US08525339B2

公开(公告)日：2013-09-03

申请号：US13191999

申请日：2011-07-27

申请人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76882 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.

摘要翻译： 提供了包含在相同开口内具有不同杂质水平的铜区域的混合互连结构。 在一个实施例中，互连结构包括具有位于其中的至少一个开口的图案化电介质材料。 双材料衬垫至少位于所述至少一个开口内的图案化电介质材料的侧壁上。 所述结构还包括具有位于所述至少一个开口的底部区域内的第一杂质水平的第一铜区域和具有位于所述至少一个开口的顶部区域内的第二杂质水平的第二铜区域和位于所述第一铜 地区。 根据本公开，第一铜区域的第一杂质水平不同于第二铜区域的第二杂质水平。

公开(公告)号：US20130175619A1

公开(公告)日：2013-07-11

申请号：US13345201

申请日：2012-01-06

申请人： Susan S. FAN ,  Balasubramanian S. HARAN ,  David V. HORAK ,  Charles W. KOBURGER, III

发明人： Susan S. FAN ,  Balasubramanian S. HARAN ,  David V. HORAK ,  Charles W. KOBURGER, III

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/42384 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78651 ,  H01L29/78654

摘要： A transistor includes a semiconductor layer, a gate spacer on the semiconductor layer, a gate dielectric comprising a first portion above the semiconductor layer and a second portion on sidewalls of the gate spacer, a work function metal layer comprising a first portion on the first portion of the gate dielectric and a second portion on sidewalls of the gate dielectric, a gate conductor on the first portion of the work function layer and abutting the second portion of the work function layer, a dielectric layer on the semiconductor layer and abutting the gate spacer, an oxide film above only one of the work function layer and the gate conductor, an oxide cap, source/drain regions, and a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions. A portion of the source/drain contact is located directly on the oxide cap.

摘要翻译： 晶体管包括半导体层，半导体层上的栅极间隔物，栅极电介质，其包括半导体层上方的第一部分和栅极间隔物的侧壁上的第二部分;功函数金属层，包括第一部分上的第一部分 并且栅极导体位于功函数层的第一部分上并邻接功函数层的第二部分，半导体层上的电介质层并与栅极间隔物邻接 仅在作用功能层和栅极导体之一上的氧化膜，氧化物盖，源极/漏极区和源极/漏极接触通过电介质层并与源极/漏极区中的一个的上表面接触 。 源极/漏极触点的一部分直接位于氧化物盖上。

公开(公告)号：US08390079B2

公开(公告)日：2013-03-05

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L27/088

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。