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    Method for Forming a Stacked FET Device
    61.
    发明公开
    Method for Forming a Stacked FET Device 审中-公开

    公开(公告)号：US20230197830A1

    公开(公告)日：2023-06-22

    申请号：US18065353

    申请日：2022-12-13

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Anne Vandooren ,  Naoto Horiguchi

    IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/40 ,  H01L21/8238

    CPC classification number: H01L29/66545 ,  H01L21/3213 ,  H01L21/31144 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/401 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/42392

    Abstract: A method for forming a stacked field-effect transistor device is provided. The method including: forming a bottom FET device comprising a bottom gate electrode arranged; forming a bonding layer of dielectric bonding material over the bottom FET device; and forming a top FET device on the bonding layer, including: forming a fin structure comprising a channel layer; etching through the bonding layer to form a bonding layer pattern comprising the dielectric bonding material underneath the fin structure; forming a dummy gate and a dummy gate spacer layer; forming cuts in the fin structure and the bonding layer pattern; forming recesses underneath a fin structure portion preserved underneath the dummy gate by laterally etching back side surface portions of a bonding layer pattern portion; removing the first spacer layer and subsequently forming a second spacer layer covering the side surfaces of the dummy gate and filling the recesses; removing the dummy gate selectively to the second spacer layer to form an upper gate cavity portion exposing the fin structure portion; forming a lower gate cavity portion exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity; and forming a gate electrode in the upper and lower gate cavity portions.

    Method for Producing a Multipixel Detector
    62.
    发明公开
    Method for Producing a Multipixel Detector 审中-公开

    公开(公告)号：US20230197761A1

    公开(公告)日：2023-06-22

    申请号：US18068775

    申请日：2022-12-20

    Applicant: IMEC VZW

    Inventor： Yunlong Li ,  Deniz Sabuncuoglu Tezcan ,  Pawel Malinowski ,  Gauri Karve

    IPC: H01L27/146

    CPC classification number: H01L27/14687 ,  H01L27/14689 ,  H01L27/14692 ,  H10K39/32

    Abstract: An example includes a method for producing a multipixel detector, the method including: providing a bottom layer including a first and a second bottom electrode, depositing an electrically insulating layer on the bottom layer, forming a first opening through the electrically insulating layer, depositing a first photon absorbing material in the first opening, forming a second opening through the electrically insulating layer, depositing a second photon absorbing material in the second opening, planarizing the deposited electrically insulating layer, the first photon absorbing material, and the second photon absorbing material to form a flat surface, and forming a common top electrode on top of the flat surface.

    VIA FORMATION IN AN INTEGRATED CIRCUIT
    63.
    发明公开
    VIA FORMATION IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20230197528A1

    公开(公告)日：2023-06-22

    申请号：US18054228

    申请日：2022-11-10

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Dunja Radisic ,  Bilal Chehab

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/522

    CPC classification number: H01L21/823871 ,  H01L27/092 ,  H01L23/5226

    Abstract: A method for forming an integrated circuit. The method includes providing a semiconductor structure comprising: (i) two transistors, (ii) a gate on the channel of the transistor, (iii) contacts coupled to each transistor, (iv) a dielectric layer over the two transistors, the gate, and the contacts, (v) a first conductive line arranged within a first metallization level and extending along a first direction, (vi) a first conductive via connecting the first conductive line with a first contact of a transistor, and (vii) a second conductive via connecting the first conductive line with a second contact of a transistor. The method also includes recessing the first dielectric layer, providing spacers along the first conductive line, depositing a second dielectric layer on the first dielectric layer, forming an opening in the second dielectric layer and first dielectric layer, and providing a conductive material in the opening, thereby forming a third conductive via.

    Multilayer Integrated Photonic Structure
    64.
    发明公开
    Multilayer Integrated Photonic Structure 审中-公开

    公开(公告)号：US20230194777A1

    公开(公告)日：2023-06-22

    申请号：US18068066

    申请日：2022-12-19

    Applicant: IMEC VZW

    Inventor： Bruno Figeys

    IPC: G02B6/12 ,  G02B6/36

    CPC classification number: G02B6/12002 ,  G02B6/3608 ,  G02B2006/12104

    Abstract: Example embodiments relate to multilayer integrated photonic structures. An example multilayer integrated photonic structure includes a propagation region formed in a first photonic layer. The propagation region includes a plurality of waveguides and a slab region in which the plurality of waveguides terminates. The multilayer integrated photonic structure also includes an outcoupling structure formed in a second photonic layer on top of the first photonic layer. The outcoupling structure is configured to couple light into and out of the multilayer integrated photonic structure. Additionally, the multilayer integrated photonic structure includes a reflector configured to optically couple the slab region of the first photonic layer and the second photonic layer. The reflector includes a first reflector element included in the slab region of the first photonic layer and a second reflector element included in the second photonic layer. The first and second reflector element are in optical communication with each other.

    Microfluidic Device and System
    66.
    发明公开
    Microfluidic Device and System 审中-公开

    公开(公告)号：US20230191411A1

    公开(公告)日：2023-06-22

    申请号：US18068779

    申请日：2022-12-20

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Chengxun Liu ,  Camila Dalben Madeira Campos ,  Xavier Rottenberg

    IPC: B01L3/00

    CPC classification number: B01L3/502761 ,  B01L3/502715 ,  B01L2200/0652 ,  B01L2300/0645 ,  B01L2400/0424 ,  B01L2300/0864

    Abstract: Embodiments for sorting particles are provided that include a microfluidic channel configured to receive a microfluidic flow that comprises a plurality of particles having different characteristics, the microfluidic channel having a plurality of output flow channels, a first detector configured to detect the location of the particles, a plurality of actuators located along the direction of the microfluidic flow and defining a sorting electrode arrangement. The microfluidic device further comprises a controller configured to receive signals from the first detector and to provide force field profiles for each of the plurality of particles, wherein each force field profile comprises a plurality of deflection force settings along the direction of the microfluidic flow. The controller individually addresses the plurality of actuators to generate a plurality of actuation inducing fields along the direction of the microfluidic flow to generate the deflection force settings in the force field profiles.

    Method for Forming a Precursor Semiconductor Device Structure
    69.
    发明公开
    Method for Forming a Precursor Semiconductor Device Structure 审中-公开

    公开(公告)号：US20230187528A1

    公开(公告)日：2023-06-15

    申请号：US18065122

    申请日：2022-12-13

    Applicant: IMEC VZW

    Inventor： Sujith Subramanian ,  Steven Demuynck ,  Hans Mertens

    IPC: H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66545

    Abstract: The disclosed method includes forming an initial layer stack comprising a sacrificial layer of a first semiconductor material and over the sacrificial layer a channel layer of a second semiconductor material, forming a fin structures by patterning trenches in the initial layer stack, forming an anchoring structure extending across the fin structures, and while the channel layers are anchored by the anchoring structure: removing the sacrificial layers by a selective etching of the first semiconductor material, thereby forming a longitudinal cavity underneath the channel layer of each fin structure, and depositing an insulating material to fill the cavities, wherein the insulating material is formed of a flowable dielectric, and subsequently recessing the at least one anchoring structure and the insulating material to a level below the cavities such that the insulating material remains in the cavities to form insulating layers underneath the channel layers of each fin structure.

    FIELD-EFFECT TRANSISTOR DEVICE
    70.
    发明公开
    FIELD-EFFECT TRANSISTOR DEVICE 审中-公开

    公开(公告)号：US20230178640A1

    公开(公告)日：2023-06-08

    申请号：US18060954

    申请日：2022-12-01

    Applicant: IMEC VZW

    Inventor： Aryan Afzalian ,  Julien Ryckaert ,  Naoto Horiguchi

    IPC: H01L29/775 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439

    Abstract: A FET device (100) is provided, the FET device including a substrate (102), a source body (120), a drain body (130) and a set of vertically spaced apart channel layers (150) extending between the source and drain body in a first direction along the substrate (102), the source body (120) comprising a common source body portion (122) arranged at a first lateral side of the set of channel layers (150) and a set of vertically spaced apart source prongs (124) protruding from the common source body portion (122) in a second direction along the substrate (102), transverse to the first direction, the drain body (130) comprising a common source body portion (132) arranged at the first lateral side of the set of channel layers (150) and a set of drain prongs (134) protruding from the common drain body portion (132) in the second direction; and a gate body (140) comprising a common gate body portion (142) arranged at a second lateral side of the channel layer (150), opposite the first lateral side, and a set of gate prongs (144) protruding from the common gate body gate portion (142) in a third direction along the substrate (102), opposite the first direction; wherein each channel layer (150) comprises a first side (150aa, 150ba) and an opposite second side (150ab, 150bb), the first side arranged in abutment with a topside or an underside of a pair of source and drain prongs (124a, 134a) and the second side (150ab, 150bb) facing a gate prong (144a, 144b).

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