公开(公告)号：US20080023728A1

公开(公告)日：2008-01-31

申请号：US11868648

申请日：2007-10-08

Applicant: Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

Inventor： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC: H01L27/10

CPC classification number: H01L27/1214 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

Abstract: Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

Abstract translation: 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

公开(公告)号：US20070241335A1

公开(公告)日：2007-10-18

申请号：US11766655

申请日：2007-06-21

Applicant: Kun-Ho KWAK ,  Jae-Hoon JANG ,  Soon-Moon JUNG ,  Won-Seok CHO ,  Hoon LIM ,  Sung-Jin KIM ,  Byung-Jun HWANG ,  Jong-Hyuk KIM

Inventor： Kun-Ho KWAK ,  Jae-Hoon JANG ,  Soon-Moon JUNG ,  Won-Seok CHO ,  Hoon LIM ,  Sung-Jin KIM ,  Byung-Jun HWANG ,  Jong-Hyuk KIM

IPC: H01L27/108

CPC classification number: H01L27/1108 ,  H01L27/11

Abstract: Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

Abstract translation: 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

公开(公告)号：US07276421B2

公开(公告)日：2007-10-02

申请号：US11197836

申请日：2005-08-05

Applicant: Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

Inventor： Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

IPC: H01L21/331

CPC classification number: H01L21/8221 ,  H01L21/28525 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L29/785

Abstract: Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.

Abstract translation: 提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。 所述方法包括在单晶半导体层上形成层间绝缘层。 形成单晶半导体插塞以穿透层间绝缘层。 使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。 结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。 也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。 单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。 通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

公开(公告)号：US07247528B2

公开(公告)日：2007-07-24

申请号：US11065750

申请日：2005-02-24

Applicant: Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

Inventor： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

IPC: H01L21/00

CPC classification number: H01L27/1108 ,  H01L27/11

Abstract: Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

Abstract translation: 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

公开(公告)号：US20060216886A1

公开(公告)日：2006-09-28

申请号：US11385473

申请日：2006-03-21

Applicant: Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

Inventor： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

Abstract translation: SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US20060115944A1

公开(公告)日：2006-06-01

申请号：US11281346

申请日：2005-11-16

Applicant: Kun-Ho Kwak ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim

Inventor： Kun-Ho Kwak ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim

IPC: H01L21/8238

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L27/092

Abstract: In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic single crystalline semiconductor plug as a seed layer. When the recessed single crystalline semiconductor plug is doped with impurities having the same conductivity type as the node impurity region, a peripheral impurity region is prevented from being counter-doped. As a result, it is possible to implement a high performance semiconductor device that requires a single crystalline thin film transistor as well as a node contact structure with ohmic contact.

Abstract translation: 在一个实施例中，使用使用节点杂质区域作为种子层的选择性外延生长工艺，形成本征单晶半导体插塞以穿过下绝缘层，并且在下绝缘层上形成单晶体半导体本体图案，使用 本征单晶半导体插头作为种子层。 当嵌入的单晶半导体插件掺杂有与节点杂质区相同的导电类型的杂质时，防止外围杂质区域被反掺杂。 结果，可以实现需要单晶薄膜晶体管的高性能半导体器件以及具有欧姆接触的节点接触结构。

公开(公告)号：US20050221544A1

公开(公告)日：2005-10-06

申请号：US11098648

申请日：2005-04-04

Applicant: Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

Inventor： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

IPC: H01L21/00 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L29/15 ,  H01L29/786 ,  H01L31/0312

CPC classification number: H01L27/1108 ,  H01L27/0688 ,  H01L27/11 ,  H01L29/78603

Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

Abstract translation: 提供制造半导体器件的方法。 层间绝缘层设置在单晶半导体衬底上。 提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。 模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。 使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。 在开口中设置单晶半导体区域。 单晶半导体区域包括单晶半导体外延图案的至少一部分。

公开(公告)号：US20180175050A1

公开(公告)日：2018-06-21

申请号：US15639733

申请日：2017-06-30

Applicant: YOUNG-HWAN SON ,  JAE-HOON JANG ,  JEE-HOON HAN

Inventor： YOUNG-HWAN SON ,  JAE-HOON JANG ,  JEE-HOON HAN

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

公开(公告)号：US20170330632A1

公开(公告)日：2017-11-16

申请号：US15664303

申请日：2017-07-31

Applicant: Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/12 ,  G11C16/10 ,  G11C16/08 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/1157

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20160284729A1

公开(公告)日：2016-09-29

申请号：US15176917

申请日：2016-06-08

Applicant: Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

Inventor： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC: H01L27/115 ,  H01L23/528 ,  G11C16/10 ,  H01L23/522 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.