公开(公告)号：US5355022A

公开(公告)日：1994-10-11

申请号：US936390

申请日：1992-08-28

申请人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  H01L21/8221 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

摘要： In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.

摘要翻译： 在叠层型半导体器件的制造方法中，首先，在层间绝缘层上形成有具有形成在其上的第一器件的第一半导体衬底，层间绝缘层形成平坦化的多晶硅层。 将第一半导体衬底和第二半导体衬底通过将多晶硅层的表面与形成在第二半导体衬底上的难熔金属层的表面紧密接触，在700℃以下进行热处理， 将难熔金属层改为硅化物。

公开(公告)号：US5338699A

公开(公告)日：1994-08-16

申请号：US10691

申请日：1993-01-29

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/76801 ,  H01L21/76834 ,  H01L27/10808 ,  Y10S257/90

摘要： A method of making a semiconductor device including a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) are smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resist film in patterning the conductive interconnection layer.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了顶部和侧壁 栅电极。 元件隔离区域（2）表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于抗蚀剂膜的过度蚀刻而导致的断开。

公开(公告)号：US5240872A

公开(公告)日：1993-08-31

申请号：US925148

申请日：1992-08-06

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L21/8242 ,  H01L23/485 ,  H01L27/108

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002

摘要： A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅极（4）的表面被第一绝缘膜（5）覆盖，左右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

公开(公告)号：US5218219A

公开(公告)日：1993-06-08

申请号：US678872

申请日：1991-04-04

申请人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。

公开(公告)号：US5194925A

公开(公告)日：1993-03-16

申请号：US657766

申请日：1991-02-21

申请人： Natsuo Ajika ,  Hideaki Arima

发明人： Natsuo Ajika ,  Hideaki Arima

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7883

摘要： A one transistor memory cell for a flash EEPROM includes: a first control gate which is disposed on a first channel region between a source region and a drain region and separated therefrom by a first insulating film; a floating gate disposed on a second channel region and is separated therefrom by a second insulating film, the floating gate disposed on the first control gate and separated therefrom by a first interlayer insulating film; and a second control gate disposed on a surface of said floating gate and separated therefrom by a second interlayer insulating film; and wherein one end of the second control gate and one end of the first control gate are electrically connected to each other through a third control gate, thereby enhancing capacity between the control gates and the floating gate.

摘要翻译： 一种用于闪存EEPROM的单晶体管存储单元包括：第一控制栅极，其设置在源极区域和漏极区域之间的第一沟道区域上，并通过第一绝缘膜与其分离; 布置在第二沟道区上并由第二绝缘膜分离的浮置栅极，所述浮置栅极设置在第一控制栅极上并由第一层间绝缘膜分离; 以及第二控制栅极，设置在所述浮置栅极的表面上并由第二层间绝缘膜分离; 并且其中第二控制栅极的一端和第一控制栅极的一端通过第三控制栅极彼此电连接，从而增强了控制栅极和浮置栅极之间的电容。

公开(公告)号：US5100818A

公开(公告)日：1992-03-31

申请号：US637423

申请日：1991-01-04

申请人： Hideaki Arima ,  Natsuo Ajika

发明人： Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region. Another part of the control gate is formed on the floating gate through an insulating film. The first impurity region is connected to a bit line and the fourth impurity region is connected to a source region respectively.

公开(公告)号：US08106443B2

公开(公告)日：2012-01-31

申请号：US12246193

申请日：2008-10-06

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/0441 ,  G11C16/0491 ,  H01L21/26586 ,  H01L29/792

摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

摘要翻译： 非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部 所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层， 形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散 肋骨中的结构是不对称的。

公开(公告)号：US08017994B2

公开(公告)日：2011-09-13

申请号：US12499220

申请日：2009-07-08

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： H01L29/792

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

公开(公告)号：US20090310409A1

公开(公告)日：2009-12-17

申请号：US12499220

申请日：2009-07-08

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： G11C16/04 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

公开(公告)号：US20090065922A1

公开(公告)日：2009-03-12

申请号：US12235734

申请日：2008-09-23

申请人： Moriyoshi NAKASHIMA ,  Kazuo Kobayashi ,  Natsuo Ajika

发明人： Moriyoshi NAKASHIMA ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC分类号： H01L23/02

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.

摘要翻译： 半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子 （22）形成在插入件（20）的上表面上。 半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和 端子（11'）。 当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。 此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。