公开(公告)号：US06696321B2

公开(公告)日：2004-02-24

申请号：US10309661

申请日：2002-12-03

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2144

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract translation: 一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。 通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。 在每个引线框架中形成的腔内部附着有硅管芯。 然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块的阵列来形成硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US06627991B1

公开(公告)日：2003-09-30

申请号：US09546053

申请日：2000-04-10

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2334

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract translation: 一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。 通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。 在每个引线框架中形成的腔内部附着有硅管芯。 然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块的阵列来形成硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US06469384B2

公开(公告)日：2002-10-22

申请号：US09776341

申请日：2001-02-01

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2348

CPC classification number: H01L23/145 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/074 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

公开(公告)号：US09053853B1

公开(公告)日：2015-06-09

申请号：US13684452

申请日：2012-11-23

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01F7/06 ,  H01F41/00

CPC classification number: H01F41/00 ,  H01F27/2804 ,  H01F27/29 ,  H01F2027/2809 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present invention relate to a method of forming a magnetics package. The method includes providing a primary coil configured to conduct a current flow; providing a substrate having a surface and a secondary coil extending from the surface, the secondary coil configured to conduct a current flow; encapsulating the secondary coil in a secondary mold compound; removing the substrate from the secondary coil, thereby leaving the secondary coil embedded in the secondary mold compound; and inductively coupling the secondary coil to the primary coil through a magnetic core, the secondary coil is electrically isolated from the primary coil, wherein a current flow in the primary coil produces a magnetic field in the magnetic core, and the magnetic field in the magnetic core induces a current flow in the secondary coil.

Abstract translation: 本发明的实施例涉及一种形成磁性封装的方法。 该方法包括提供构造成传导电流的初级线圈; 提供具有表面的基板和从表面延伸的次级线圈，所述次级线圈构造成导通电流; 将次级线圈封装在二次模具化合物中; 从次级线圈移除基板，从而使次级线圈嵌入在二次模具化合物中; 并且通过磁芯将次级线圈感应耦合到初级线圈，次级线圈与初级线圈电隔离，其中初级线圈中的电流在磁芯中产生磁场，并且磁场中的磁场 芯在次级线圈中感应出电流。

公开(公告)号：US08609978B2

公开(公告)日：2013-12-17

申请号：US12069094

申请日：2008-02-06

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L31/042

CPC classification number: H01L31/044 ,  H01L31/052 ,  H01L31/0521 ,  H01L31/054 ,  H01L31/0543 ,  Y02E10/52 ,  Y10T29/49002

Abstract: A leadframe based photovoltaic assembly and method for assembling the same is disclosed. The photovoltaic assembly comprises a first and second mold compounds to effectuate the accurate placement of an optical concentrator above a photovoltaic cell. The photovoltaic assembly is able to be assembled using existing mature semiconductor packaging technologies.

Abstract translation: 公开了一种基于引线框的光伏组件及其组装方法。 光伏组件包括第一和第二模具化合物，以实现光聚焦器在光伏电池上方的精确放置。 光伏组件能够使用现有的成熟半导体封装技术进行组装。

公开(公告)号：US08524532B1

公开(公告)日：2013-09-03

申请号：US13406257

申请日：2012-02-27

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/00

CPC classification number: H01L27/088 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L27/0629 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1306 ,  H05K1/186 ,  H05K3/4661 ,  H01L2924/00

Abstract: One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.

Abstract translation: 本发明的一个方面涉及具有嵌入式功率级的集成电路封装。 集成电路封装包括彼此电耦合的第一场效应晶体管（FET）和第二FET。 FET被嵌入在由多个电介质层形成的电介质基板中。 电介质层与一个或多个箔层压在一起，这些箔层有助于形成用于封装的电互连。 各种实施例涉及形成上述包装的方法。

公开(公告)号：US08183088B2

公开(公告)日：2012-05-22

申请号：US12823411

申请日：2010-06-25

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Byoung-Ok Lee

IPC: H01L21/00

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US20120064667A1

公开(公告)日：2012-03-15

申请号：US13297938

申请日：2011-11-16

Applicant: Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

Inventor： Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

IPC: H01L21/50

CPC classification number: H01L23/49575 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract translation: 公开了一种能够安装在母板上的半导体管芯封装。 半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。 半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。 基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。 第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

公开(公告)号：US07772681B2

公开(公告)日：2010-08-10

申请号：US11471291

申请日：2006-06-19

Applicant: Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer

Inventor： Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer

IPC: H01L21/495

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US07582956B2

公开(公告)日：2009-09-01

申请号：US11693141

申请日：2007-03-29

Applicant: Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

Inventor： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC: H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract translation: 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。