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    Spatial light modulator with four transistor electrode driver
    61.
    发明授权
    Spatial light modulator with four transistor electrode driver 有权
    具有四个晶体管电极驱动器的空间光调制器

    公开(公告)号：US07443716B2

    公开(公告)日：2008-10-28

    申请号：US11282056

    申请日：2005-11-16

    申请人： Thu Nguyen

    发明人： Thu Nguyen

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator. The memory cell includes a first PMOS transistor, wherein a source of the first PMOS transistor is coupled to a first supply voltage. The memory cell also includes a first NMOS transistor, wherein a drain of the first NMOS transistor is coupled to a drain of the first PMOS transistor, a source of the first NMOS transistor is coupled to a second supply voltage, and a gate of the first NMOS transistor is coupled to a gate of the first PMOS transistor. The memory cell further includes a second transistor adapted to establish a conduction path between the gate of the first NMOS transistor and at least one of the first supply voltage or the second supply voltage. Moreover, the memory includes a select transistor, wherein a drain of the select transistor is coupled to the gate of the first NMOS transistor and wherein the memory cell is free from a connection to a fifth transistor.

    摘要翻译： 用于驱动与空间光调制器的微镜相关联的互补电极对的存储单元。 存储单元包括第一PMOS晶体管，其中第一PMOS晶体管的源极耦合到第一电源电压。 存储单元还包括第一NMOS晶体管，其中第一NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极，第一NMOS晶体管的源极耦合到第二电源电压，第一NMOS晶体管的栅极 NMOS晶体管耦合到第一PMOS晶体管的栅极。 存储单元还包括适于在第一NMOS晶体管的栅极与第一电源电压或第二电源电压中的至少一个之间建立导电路径的第二晶体管。 此外，存储器包括选择晶体管，其中选择晶体管的漏极耦合到第一NMOS晶体管的栅极，并且其中存储单元没有与第五晶体管的连接。

    Transducer including an element of a transducer and a sidewall in an electrically conductive magnetic layer
    63.
    发明申请
    Transducer including an element of a transducer and a sidewall in an electrically conductive magnetic layer 有权
    传感器，其包括换能器的元件和导电磁性层中的侧壁

    公开(公告)号：US20070177300A1

    公开(公告)日：2007-08-02

    申请号：US11344398

    申请日：2006-01-31

    申请人： Huaqing Yin ,  David Seets ,  Thu Nguyen

    发明人： Huaqing Yin ,  David Seets ,  Thu Nguyen

    IPC分类号： G11B5/147

    CPC分类号： G11B5/3163 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/313 ,  Y10T29/49021

    摘要： A transducer includes a first layer that is selectively deposited in a contact region to form a core, and selectively deposited in a transducer region to form a first element of the transducer. The transducer includes an electrically conductive magnetic deposit. The electrically conductive magnetic deposit forms a sidewall on the core. The electrically conductive magnetic deposit forms a second element of the transducer in the transducer region. The second element of the transducer has a planarized surface that is coplanar with a planarized surface of the sidewall.

    摘要翻译： 换能器包括选择性地沉积在接触区域中以形成芯并且选择性地沉积在换能器区域中以形成换能器的第一元件的第一层。 换能器包括导电磁性沉积物。 导电磁性沉积物在芯上形成侧壁。 导电磁性沉积物在换能器区域中形成换能器的第二元件。 换能器的第二元件具有与侧壁的平坦化表面共面的平坦化表面。

    HMGA alleles and use of the same as genetic markers for growth, fatness, meat quality, and feed efficiency traits
    64.
    发明授权
    HMGA alleles and use of the same as genetic markers for growth, fatness, meat quality, and feed efficiency traits 失效
    HMGA等位基因和使用与生长，脂肪，肉质和饲料效率性状的遗传标记相同

    公开(公告)号：US07244564B2

    公开(公告)日：2007-07-17

    申请号：US10388703

    申请日：2003-03-14

    申请人： Max F. Rothschild ,  Kwan-Suk Kim ,  Nguyet Thu Nguyen

    发明人： Max F. Rothschild ,  Kwan-Suk Kim ,  Nguyet Thu Nguyen

    IPC分类号： C12O1/70 ,  C12P19/34

    CPC分类号： C12Q1/6876 ,  C12Q2600/156

    摘要： Disclosed herein are genetic markers for animal growth, fatness, meat quality, and feed efficiency, methods for identifying such markers, and methods of screening animals to determine those more likely to produce desired growth, fatness, meat quality, and feed efficiency and preferably selecting those animals for future breeding purposes. The markers are based upon the presence or absence of certain polymorphisms in an HMGA nucleotide sequence.

    摘要翻译： 本文公开了用于动物生长，脂肪，肉质量和饲料效率的遗传标记，用于鉴定这些标记的方法，以及筛选动物以确定更可能产生所需生长，脂肪，肉质和进食效率的方法，优选选择 这些动物为未来繁殖的目的。 标记基于HMGA核苷酸序列中某些多态性的存在或不存在。

    System and method having strapping with override functions
    66.
    发明申请
    System and method having strapping with override functions 有权
    具有覆盖功能的系统和方法

    公开(公告)号：US20050038987A1

    公开(公告)日：2005-02-17

    申请号：US10641103

    申请日：2003-08-15

    申请人： James Sweet ,  Thu Nguyen

    发明人： James Sweet ,  Thu Nguyen

    IPC分类号： H04N5/44 ,  H04N5/46 ,  H04N5/913 ,  G06F9/00

    CPC分类号： H04N21/426 ,  H04N5/4401 ,  H04N5/46 ,  H04N7/035 ,  H04N21/4263 ,  H04N2005/91364

    摘要： A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be temporary. The changing of the state or mode of the device can be used to perform testing of the chip, during which a memory is written to and read from to verify operation of the chip. The second state or mode of the device may also be used to allow the device to perform alternative functions that are not available during its first state or mode.

    摘要翻译： 系统和方法允许覆盖捆绑选项。 捆扎信号将设备（例如，处理器）置于第一状态或模式（例如，客户端或主机）。 覆盖系统将设备置于第二状态或模式。 第二种状态或模式可以是临时的。 可以使用设备的状态或模式的改变来执行芯片的测试，在此期间，存储器被写入和读取以验证芯片的操作。 设备的第二状态或模式也可以用于允许设备执行在其第一状态或模式期间不可用的替代功能。

    Synchronized seismic signal acquisition method and device
    68.
    发明授权
    Synchronized seismic signal acquisition method and device 失效
    同步地震信号采集方法及装置

    公开(公告)号：US06253156B1

    公开(公告)日：2001-06-26

    申请号：US09460514

    申请日：1999-12-14

    申请人： Van Bui-Tran ,  Thi Thu Nguyen ,  Gérard Thierry

    发明人： Van Bui-Tran ,  Thi Thu Nguyen ,  Gérard Thierry

    IPC分类号： G01V128

    CPC分类号： G01V1/32 ,  G01V1/26 ,  G01V2210/48

    摘要： Method and device intended for synchronized acquisition of seismic signals by one or more acquisition units suited for seismic signal digitizing, allowing to obtain, for each signal, a series y[n] of samples of these signals readjusted from a reference time on, from a first series x[n] of digitized samples of this seismic signal produced from any initial time prior to the reference time. The method essentially comprises detecting a synchronization signal indicative of this reference time (TR), measuring the effective time difference (D) between the reference time and the initial time, determining coefficients of a digital filter (F) suited to compensate for the fractional part (d) of the measured effective time difference, and applying this compensation digital filter to the first series of samples, which allows to obtain a series of digitized samples readjusted from the reference time. In order to accelerate determination of the filter coefficients depending on the difference D observed, the coefficients of a certain number of intermediate filters corresponding to determined fractions of the sampling interval are preferably precalculated. The method can be applied for seismic prospecting or monitoring, earthquake detection, etc.

    摘要翻译： 用于通过适合于地震信号数字化的一个或多个采集单元来同步采集地震信号的方法和装置，允许从每个信号获得从参考时间开始从这些信号重新调整的这些信号的一系列y [n]样本 从参考时间之前的任何初始时间产生的该地震信号的数字化样本的第一系列x [n]。 该方法基本上包括检测指示该参考时间（TR）的同步信号，测量参考时间和初始时间之间的有效时间差（D），确定适于补偿分数部分的数字滤波器（F）的系数 （d）测量的有效时间差，并将该补偿数字滤波器应用于第一系列样本，这允许从参考时间重新调整一系列数字化采样。 为了根据观察到的差异D加速滤波器系数的确定，优选地对与取样间隔的确定分数相对应的一定数量的中间滤波器的系数进行预先计算。 该方法可应用于地震勘探或监测，地震检测等。

    Integrated circuit structure having a capacitor structured to reduce dishing of metal layers
    69.
    发明授权
    Integrated circuit structure having a capacitor structured to reduce dishing of metal layers 有权
    具有电容器的集成电路结构，其构造为减少金属层的凹陷

    公开(公告)号：US08878337B1

    公开(公告)日：2014-11-04

    申请号：US13186279

    申请日：2011-07-19

    申请人： Hong-Tsz Pan ,  Yun Wu ,  Shuxian Wu ,  Qi Lin ,  Bang-Thu Nguyen

    发明人： Hong-Tsz Pan ,  Yun Wu ,  Shuxian Wu ,  Qi Lin ,  Bang-Thu Nguyen

    IPC分类号： H01L21/02

    CPC分类号： H01L29/94 ,  H01L21/3212 ,  H01L21/823842 ,  H01L27/0629 ,  H01L29/66181 ,  H01L29/66545 ,  H01L29/78

    摘要： A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.

    摘要翻译： 一种用于减轻由化学机械抛光引起的金属栅极凹陷的方法和集成电路结构。 集成电路结构包括包括至少一个第一类型装置的第一区域; 第二区域，包括至少一个第二类型装置; 第三区域包括至少一个具有多晶硅最上层的电容器，其中电容器面积大于第一和第二区域的总和。 该方法利用电容器的多晶硅来减轻至少一个器件的金属栅极的金属栅极凹陷。

    Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist
    70.
    发明授权
    Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist 有权
    用于设计和构造具有电压辅助功能的多端口存储器电路的方法和装置

    公开(公告)号：US08760958B2

    公开(公告)日：2014-06-24

    申请号：US13421704

    申请日：2012-03-15

    申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

    发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

    IPC分类号： G11C8/00 ,  G11C8/16

    CPC分类号： G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

    摘要： To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

    摘要翻译： 为了处理多个并发存储器请求，提出了一个双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问位单元的真实侧和假侧。 单端读取允许内存系统同时处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 位单元格。 因此，具有电压辅助的单端操作允许存储器系统处理两个并行写入操作。 可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。