公开(公告)号：US06171936B2

公开(公告)日：2001-01-09

申请号：US09224720

申请日：1999-01-04

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L2120

CPC分类号： H01L23/522 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/8258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure including a silicon wafer having silicon regions, and at least one GexSi1−x region integrated within the silicon regions. The silicon and GexSi1−x regions can be substantially coplanar surfaces. The structure can include at least one electronic device configured in the silicon regions, and at least one electronic device of III-V materials configured in said at least one GexSi1−x region. The structure can be, for example, an integrated III-V/Si semiconductor microchip. In accordance with another embodiment of the invention there is provided a method of fabricating a semiconductor structure, including providing a silicon wafer with a surface; forming a pattern of vias within the surface of the wafer; and depositing regions of GexSi1−x within the vias. The method can include the step of processing the wafer so that the wafer and GexSi1−x regions have substantially coplanar surfaces. Another embodiment provides a method of fabricating a semiconductor structure, including providing a silicon wafer with a surface; depositing regions of GexSi1−x to the surface of the silicon wafer; and depositing silicon to the surface such that the deposited GexSi1−x regions are integrated within silicon.

摘要翻译： 包括具有硅区域的硅晶片和集成在硅区域内的至少一个GexSi1-x区域的半导体结构。 硅和GexSi1-x区域可以是基本上共面的表面。 该结构可以包括配置在硅区域中的至少一个电子器件，以及配置在所述至少一个GexSi1-x区域中的至少一个III-V材料的电子器件。 该结构可以是例如集成的III-V / Si半导体微芯片。 根据本发明的另一个实施例，提供一种制造半导体结构的方法，包括提供具有表面的硅晶片; 在晶片的表面内形成通孔图案; 并在通孔内沉积GexSi1-x的区域。 该方法可以包括处理晶片的步骤，使得晶片和GexSi1-x区域具有基本上共面的表面。 另一实施例提供一种制造半导体结构的方法，包括提供具有表面的硅晶片; 将GexSi1-x的区域沉积到硅晶片的表面; 并将硅沉积到表面上，使得沉积的GexSi1-x区域集成在硅中。

公开(公告)号：US6039803A

公开(公告)日：2000-03-21

申请号：US806741

申请日：1997-02-27

申请人： Eugene A. Fitzgerald ,  Srikanth B. Samavedam

发明人： Eugene A. Fitzgerald ,  Srikanth B. Samavedam

IPC分类号： C30B25/18 ,  H01L21/20

CPC分类号： C30B25/18 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  Y10S117/902

摘要： A method of processing semiconductor materials, including providing a monocrystalline silicon substrate having a (001) crystallographic surface orientation; off-cutting the substrate to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and epitaxially growing a relaxed graded layer of a crystalline GeSi on the substrate. A semiconductor structure including a monocrystalline silicon substrate having a (001) crystallographic surface orientation, the substrate being off-cut to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and a relaxed graded layer of a crystalline GeSi which is epitaxially grown on the substrate.

摘要翻译： 一种处理半导体材料的方法，包括提供具有（001）晶面取向的单晶硅衬底; 将基板切割成朝向[110]方向偏移约2°至约6°的取向; 并且在衬底上外延生长结晶GeSi的缓和梯度层。 一种半导体结构，其包括具有（001）结晶表面取向的单晶硅衬底，所述衬底偏离朝向[110]方向偏移约2度至约6度的取向; 以及在衬底上外延生长的结晶GeSi的弛豫梯度层。

公开(公告)号：US20160380145A1

公开(公告)日：2016-12-29

申请号：US14612677

申请日：2015-02-03

申请人： Eugene A. Fitzgerald ,  Arthur J. Pitera ,  Steven A. Ringel

发明人： Eugene A. Fitzgerald ,  Arthur J. Pitera ,  Steven A. Ringel

IPC分类号： H01L31/18 ,  H01L31/0304 ,  H01L31/02 ,  H01L31/0735

CPC分类号： H01L31/184 ,  H01L31/02008 ,  H01L31/02167 ,  H01L31/0304 ,  H01L31/0336 ,  H01L31/0735 ,  H01L31/075 ,  H01L31/076 ,  Y02E10/544 ,  Y02E10/548

摘要： Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 107 cm−2, and forming, over the first junction, a cap layer comprising silicon, wherein the substrate consists essentially of silicon.

摘要翻译： 用于形成太阳能电池的方法包括在衬底上形成包含至少一种III-V材料并且具有小于约107cm -2的穿透位错密度的第一结，并且在第一结上形成包括 硅，其中所述衬底基本上由硅组成。

公开(公告)号：US09219065B2

公开(公告)日：2015-12-22

申请号：US12573589

申请日：2009-10-05

申请人： Eugene A. Fitzgerald ,  Nicole Gerrish

发明人： Eugene A. Fitzgerald ,  Nicole Gerrish

IPC分类号： H01L29/72 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material.

摘要翻译： 制造包括nMOSFET的电路的方法包括提供衬底，在衬底上沉积包含锗的应变诱导材料，以及在衬底上集成pMOSFET，pMOSFET包括表面粗糙度小于1nm的应变通道。 应变诱导材料接近并与pMOSFET通道接触，pMOSFET通道中的应变由应变诱导材料诱导，并且pMOSFET的源极和漏极在应变诱导中至少部分地形成 材料。

公开(公告)号：US08120060B2

公开(公告)日：2012-02-21

申请号：US11591383

申请日：2006-11-01

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L29/66

CPC分类号： H01L27/14601 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/76254 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/144 ,  H01L27/1446 ,  H01L27/14683 ,  H01L27/15 ,  H01L27/156 ,  H01L31/0328 ,  H01L31/143 ,  H01L31/162 ,  H01L2924/0002 ,  Y10S438/933 ,  H01L2924/00

摘要： Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure also includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device comprising an element including at least a portion of the monocrystalline silicon layer. The structure includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure also includes at least one III-V electronic device comprising an element including at least a portion of the second monocrystalline semiconductor layer.

摘要翻译： 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。 在一种结构中，单片集成半导体器件结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。 该结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层和设置在第一区域中的绝缘层上的单晶硅层。 该结构包括至少一个硅基电子器件，其包含至少部分单晶硅层的元件。 该结构包括第二单晶半导体层，其设置在第二区域中的第一单晶半导体层的至少一部分上且不存在于第一区域中，其中第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。 该结构还包括至少一个III-V电子器件，其包括包含第二单晶半导体层的至少一部分的元件。

公开(公告)号：US08063413B2

公开(公告)日：2011-11-22

申请号：US12265976

申请日：2008-11-06

申请人： Yu Bai ,  Minjoo L. Lee ,  Eugene A. Fitzgerald

发明人： Yu Bai ,  Minjoo L. Lee ,  Eugene A. Fitzgerald

IPC分类号： H01L29/15

CPC分类号： H01L21/0251 ,  B82Y10/00 ,  H01L21/02395 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02535 ,  H01L29/1054 ,  Y10S438/933 ,  Y10S438/938

摘要： A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers.

摘要翻译： 提供半导体结构。 半导体结构包括一个或多个III-IV材料基半导体层。 在一个或多个III-IV材料基半导体层上形成拉伸应变Ge层。 拉伸应变Ge层通过在一个或多个III-IV材料基半导体层上的晶格失配的异质外延产生。

公开(公告)号：US07846802B2

公开(公告)日：2010-12-07

申请号：US11848642

申请日：2007-08-31

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Richard Hammond ,  Eugene A. Fitzgerald

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Richard Hammond ,  Eugene A. Fitzgerald

IPC分类号： H01L21/00

CPC分类号： H01L29/1054 ,  H01L29/105 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7842 ,  Y10S438/926

摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

摘要翻译： 包括具有无杂质区域的应变材料层的半导体结构和器件及其制造方法。 应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。 当杂质存在于应变材料层的某些区域中时，器件性能下降。 通过采用具有所描述或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。

公开(公告)号：US20100221512A1

公开(公告)日：2010-09-02

申请号：US12395564

申请日：2009-02-27

申请人： Kenneth E. Lee ,  Eugene A. Fitzgerald

发明人： Kenneth E. Lee ,  Eugene A. Fitzgerald

IPC分类号： B32B7/02 ,  B05D1/36

CPC分类号： H01L21/02543 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0262 ,  Y10T428/2495

摘要： Digital metamorphic alloy (DMA) buffer structures for transitioning from a bottom crystalline layer to a lattice mismatched top crystalline layer, and methods for manufacturing such layers are described. In some embodiments, a layered crystalline structure includes a first layer of a first crystalline material having a first in-plane lattice constant and a second layer of a second crystalline material disposed over the first layer and having a second in-plane lattice constant that is lattice mismatched with the first crystalline material. Multiple sets of buffer layers may be disposed between the first layer and the second layer. Each set is a digital metamorphic alloy including a buffer layer of a third crystalline material and a buffer layer of a fourth crystalline material where an effective in-plane lattice constant of each set falls between the first lattice of the first layer and the second lattice constant of the second layer.

摘要翻译： 描述了从底部结晶层转变为晶格失配顶部晶体层的数字变质合金（DMA）缓冲结构以及制造这种层的方法。 在一些实施例中，层状晶体结构包括具有第一面内晶格常数的第一晶体材料的第一层和设置在第一层上并具有第二平面晶格常数的第二晶体材料的第二层， 晶格与第一结晶材料不匹配。 可以在第一层和第二层之间设置多组缓冲层。 每组是包含第三结晶材料的缓冲层和第四晶体材料的缓冲层的数字变质合金，其中每组的有效面内晶格常数落在第一层的第一晶格和第二晶格常数之间 的第二层。

公开(公告)号：US20100116329A1

公开(公告)日：2010-05-13

申请号：US12474877

申请日：2009-05-29

申请人： Eugene A. Fitzgerald ,  Arthur J. Pitera ,  Steven A. Ringel

发明人： Eugene A. Fitzgerald ,  Arthur J. Pitera ,  Steven A. Ringel

IPC分类号： H01L31/00 ,  H01L31/0304

CPC分类号： H01L31/184 ,  H01L31/02008 ,  H01L31/02167 ,  H01L31/0304 ,  H01L31/0336 ,  H01L31/0735 ,  H01L31/075 ,  H01L31/076 ,  Y02E10/544 ,  Y02E10/548

摘要： Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 107 cm−2, and forming, over the first junction, a cap layer comprising silicon, wherein the substrate consists essentially of silicon.

摘要翻译： 用于形成太阳能电池的方法包括在衬底上形成包含至少一种III-V材料并且具有小于约107cm -2的穿透位错密度的第一结，并且在第一结上形成包括 硅，其中所述衬底基本上由硅组成。

公开(公告)号：US07705370B2

公开(公告)日：2010-04-27

申请号：US11591658

申请日：2006-11-01

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L31/0328

CPC分类号： H01L27/14601 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/76254 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/144 ,  H01L27/1446 ,  H01L27/14683 ,  H01L27/15 ,  H01L27/156 ,  H01L31/0328 ,  H01L31/143 ,  H01L31/162 ,  H01L2924/0002 ,  Y10S438/933 ,  H01L2924/00

摘要： Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer.

摘要翻译： 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。 在一种结构中，单片集成半导体器件结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。 该结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层和设置在第一区域中的绝缘层上的单晶硅层。 该结构包括至少一个硅基光电检测器，其包括至少部分单晶硅层的有源区。 该结构还包括第二单晶半导体层，其设置在第二区域中的第一单晶半导体层的至少一部分上且不存在于第一区域中，其中第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数 。 该结构包括至少一个非硅光电检测器，其包括包括第二单晶半导体层的至少一部分的有源区。