公开(公告)号：US07326610B2

公开(公告)日：2008-02-05

申请号：US11271032

申请日：2005-11-10

申请人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

发明人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

IPC分类号： H01L21/31

CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823835

摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

摘要翻译： 硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。 将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或 现有的金属门。 硅化物用作连接CMOS结构的PFET和NFET器件的选项。 该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。 提供了具有栅极和源极和漏极区域的半导体衬底。 栅极电介质层与金属栅极层一起沉积在衬底上。 然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。 可以在栅极内使用第二硅化物。 在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

公开(公告)号：US07217655B2

公开(公告)日：2007-05-15

申请号：US11047652

申请日：2005-02-02

申请人： Cyril Cabral, Jr. ,  Stefanie R. Chiras ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Andrew J. Kellock ,  Judith M. Rubino ,  Roger Y. Tsai

发明人： Cyril Cabral, Jr. ,  Stefanie R. Chiras ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Andrew J. Kellock ,  Judith M. Rubino ,  Roger Y. Tsai

IPC分类号： H01L21/4763

CPC分类号： H01L21/2885 ,  C25D9/08 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2224/05007

摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

公开(公告)号：US07151023B1

公开(公告)日：2006-12-19

申请号：US11161372

申请日：2005-08-01

申请人： Hasan M. Nayfeh ,  Mahender Kumar ,  Sunfei Fang ,  Jakub T Kedzierski ,  Cyril Cabral, Jr.

发明人： Hasan M. Nayfeh ,  Mahender Kumar ,  Sunfei Fang ,  Jakub T Kedzierski ,  Cyril Cabral, Jr.

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/4763 ,  H01L29/00

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.

摘要翻译： 描述了MOSFET结构和形成方法。 该方法包括形成足够厚的含金属层，以将半导体栅极堆叠完全转换成第一MOSFET型区域中的半导体金属合金，但是仅仅足够厚以将第二半导体栅极堆叠部分地转换成半导体金属合金 MOSFET类型区域。 在一个实施例中，在形成含金属层之前，第一MOSFET区域中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，含金属层相对于另一个MOSFET区域在一个MOSFET区域上变薄。

公开(公告)号：US07029966B2

公开(公告)日：2006-04-18

申请号：US10605261

申请日：2003-09-18

申请人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

发明人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823835

摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

摘要翻译： 硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。 将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或 现有的金属门。 硅化物用作连接CMOS结构的PFET和NFET器件的选项。 该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。 提供了具有栅极和源极和漏极区域的半导体衬底。 栅极电介质层与金属栅极层一起沉积在衬底上。 然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。 可以在栅极内使用第二硅化物。 在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

公开(公告)号：US07023064B2

公开(公告)日：2006-04-04

申请号：US10710063

申请日：2004-06-16

申请人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

发明人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

IPC分类号： H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

公开(公告)号：US06700203B1

公开(公告)日：2004-03-02

申请号：US09686742

申请日：2000-10-11

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L2348

CPC分类号： H01L28/20 ,  H01L27/0688

摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

摘要翻译： 公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。 具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通 以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

公开(公告)号：US06437440B1

公开(公告)日：2002-08-20

申请号：US09759258

申请日：2001-01-16

申请人： Cyril Cabral, Jr. ,  Patrick William Dehaven ,  Daniel Charles Edelstein ,  David Peter Klaus ,  James Manley Pollard, III ,  Carol L. Stanis ,  Cyprian Emeka Uzoh

发明人： Cyril Cabral, Jr. ,  Patrick William Dehaven ,  Daniel Charles Edelstein ,  David Peter Klaus ,  James Manley Pollard, III ,  Carol L. Stanis ,  Cyprian Emeka Uzoh

IPC分类号： H01L2940

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/12 ,  H01L29/4933 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

摘要翻译： 描述了用于电互连的互连结构和阻挡层，其结合了诸如Cu的第一材料和诸如Al，W和PbSn的第二材料之间的六方相中的TaN层。 六方相中的TaN多层和α相中的Ta也被描述为阻挡层。 本发明克服了在500℃的温度退火期间将Cu扩散到期望分离的材料中的问题。

公开(公告)号：US06344129B1

公开(公告)日：2002-02-05

申请号：US09418197

申请日：1999-10-13

申请人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

发明人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

IPC分类号： C25D500

CPC分类号： C25D5/10 ,  C25D3/38 ,  C25D5/00 ,  C25D7/123 ,  C25D21/02 ,  H05K3/423

摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.

摘要翻译： 公开了一种在电子基板上镀铜导体的方法和形成的器件。 在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。 然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。 双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如双镶嵌结构中的通孔，其直径/深度的纵横比大于1/3或高达{分数（ 1/10）}。 各种电镀参数用于在单步沉积或双步沉积工艺中提供短电阻瞬变。 这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

公开(公告)号：US06187679B1

公开(公告)日：2001-02-13

申请号：US08807739

申请日：1997-02-26

申请人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

IPC分类号： H01L2144

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665

摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.

摘要翻译： 低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。 钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。 用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600-700℃之间

公开(公告)号：US5828131A

公开(公告)日：1998-10-27

申请号：US586046

申请日：1996-01-16

申请人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

IPC分类号： C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665

摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900.degree. C., and more preferably between about 600.degree.-700.degree. C.

摘要翻译： 低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。 钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。 用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600℃至700℃之间。