公开(公告)号：US09425318B1

公开(公告)日：2016-08-23

申请号：US14633351

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Gerd Zschaetzsch

IPC: H01L21/324 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L21/02 ,  H01L27/108 ,  H01L29/423 ,  H01L27/092 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括形成堆叠在衬底上的叠层。 堆叠包括硅锗层和硅层，其中硅锗层具有第一锗浓度。 堆叠被冷凝以在锗层中产生第二锗浓度，其中第二锗浓度大于第一锗浓度。 形成包括叠层的翅片，并且形成覆盖在翅片上的浇口。

公开(公告)号：US09406565B2

公开(公告)日：2016-08-02

申请号：US13842077

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一牺牲氧化物层被形成在半导体衬底上，并且第一注入掩模被图案化成覆盖在第一牺牲氧化物层上以暴露与栅电极结构相邻的第一牺牲氧化物层的一部分。 电导率确定离子通过第一牺牲氧化物层注入到半导体衬底中。 在将导电性确定离子注入半导体衬底之后，去除第一注入掩模和第一牺牲氧化物层。

公开(公告)号：US09396950B2

公开(公告)日：2016-07-19

申请号：US14184863

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer ,  Alban Zaka

IPC: H01L21/336 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed.

Abstract translation: 在本发明的方面中，公开了一种形成半导体器件的方法，其中在制造期间的早期形成非晶区域，并且非晶区域在随后的处理序列期间保守，并且提供具有非晶区域的中间半导体器件结构 在制造的早期阶段。 这里，在半导体衬底上提供栅极结构，并且在栅极结构附近形成非晶区。 源极/漏极延伸区域或源极/漏极区域形成在非晶区域中。 在一些说明性实施例中，可以将氟注入到非晶区域中。 在形成源极/漏极延伸区域和/或源极/漏极区域之后，执行快速热退火工艺。

公开(公告)号：US09391156B2

公开(公告)日：2016-07-12

申请号：US14471546

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L49/02 ,  H01L21/28 ,  H01L29/49 ,  H01L27/06 ,  H01L23/522

CPC classification number: H01L29/4983 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28132 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

Abstract translation: 提供一种制造半导体器件的方法，包括在半导体衬底上形成虚设晶体管器件的栅电极，在栅极上形成高k材料层并在栅极上形成高k材料层，并在高k材料上形成金属层 层叠并与栅电极相邻以形成电容器。

公开(公告)号：US09324831B2

公开(公告)日：2016-04-26

申请号：US14461713

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/66575 ,  H01L29/66651

Abstract: Methods for forming gates without spacers and the resulting devices are disclosed. Embodiments may include forming a channel layer on a substrate; forming a dummy gate on the channel layer; forming an interlayer dielectric (ILD) on the channel layer and surrounding the dummy gate; forming a trench within the ILD and the channel layer by removing the dummy gate and the channel layer below the dummy gate; forming an un-doped channel region at the bottom of the trench; and forming a gate above the un-doped channel region within the trench.

Abstract translation: 公开了用于形成没有间隔物的栅极和所得到的器件的方法。 实施例可以包括在衬底上形成沟道层; 在通道层上形成一个虚拟栅极; 在沟道层上形成层间电介质（ILD）并围绕虚拟栅极; 通过去除虚拟栅极以下的虚拟栅极和沟道层，在ILD和沟道层内形成沟槽; 在沟槽的底部形成未掺杂沟道区; 以及在沟槽内的未掺杂沟道区上方形成栅极。

公开(公告)号：US20160064471A1

公开(公告)日：2016-03-03

申请号：US14471546

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L49/02 ,  H01L21/28 ,  H01L29/49 ,  H01L27/06

CPC classification number: H01L29/4983 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28132 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

Abstract translation: 提供一种制造半导体器件的方法，包括在半导体衬底上形成虚设晶体管器件的栅电极，在栅极上形成高k材料层并在栅极上形成高k材料层，并在高k材料上形成金属层 层叠并与栅电极相邻以形成电容器。

公开(公告)号：US20160005734A1

公开(公告)日：2016-01-07

申请号：US14856065

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L29/10

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer.

Abstract translation: 公开了一种集成电路产品，其包括具有第一PMOS有源区和第二PMOS有源区的半导体衬底，其中仅第二PMOS有源区具有形成于其上的锗锗层，形成在第一PMOS有源区和第二PMOS有源区之上的第一PMOS器件 PMOS有源区，第一PMOS器件具有第一栅极结构，以及形成在第二PMOS有源区中和上方的第二PMOS器件，第二PMOS器件具有设置在硅锗层上的第二栅极结构。

公开(公告)号：US09231045B2

公开(公告)日：2016-01-05

申请号：US13874200

申请日：2013-04-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括第一晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第一功函数材料层，设置在第一功函数材料层上的第二功函数材料层，以及 设置在第二功函数材料层上的金属填充材料。 集成电路还包括第二晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第二功函件层，以及设置在第二功函数材料上的金属填充材料层 层。 此外，集成电路包括电阻器结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的金属填充材料层以及设置在金属填充材料层上的硅材料层。

公开(公告)号：US09218976B2

公开(公告)日：2015-12-22

申请号：US13965860

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Gerd Zschaetzsch ,  Jan Hoentschel

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L21/28097 ,  H01L21/8238 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/6659

Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 然而，完全硅化的栅极的形成受到源极和漏极区域以及栅极电极的硅化同时正常执行的事实的阻碍。 所要求保护的方法提出了两个相互连接的硅化过程。 在第一硅化工艺期间，形成金属硅化物，形成与源区和漏区的界面，而不影响栅电极。 在第二硅化处理期间，形成与栅电极具有界面的金属硅化物层，而不会影响晶体管的源极和漏极区域。

公开(公告)号：US20150228490A1

公开(公告)日：2015-08-13

申请号：US14698103

申请日：2015-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Jan Hoentschel ,  Steven Langdon

IPC: H01L21/265 ,  H01L21/8234 ,  H01L21/266

CPC classification number: H01L21/26506 ,  H01L21/266 ,  H01L21/2822 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517

Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.

Abstract translation: 复杂晶体管的性能和/或均匀性可以通过在形成复杂的高k金属栅电极结构之前在晶体管的有源区中引入碳物种来增强。 例如，在选择性地形成用于P沟道晶体管的阈值调节半导体材料之后，可以通过离子注入将碳物质并入P沟道晶体管和N沟道晶体管的有源区，而N的有源区 通道晶体管仍然被掩蔽。