公开(公告)号：US20160035728A1

公开(公告)日：2016-02-04

申请号：US14882308

申请日：2015-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。

公开(公告)号：US09245981B2

公开(公告)日：2016-01-26

申请号：US14808914

申请日：2015-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Ali Khakifirooz ,  Edward J. Nowak ,  Kern Rim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/785

Abstract: An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.

公开(公告)号：US09236463B2

公开(公告)日：2016-01-12

申请号：US14027563

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/10 ,  H01L29/205 ,  H01L29/20 ,  H01L29/51

CPC classification number: H01L29/778 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/205 ,  H01L29/4232 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

公开(公告)号：US09214553B2

公开(公告)日：2015-12-15

申请号：US14200952

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 所公开的一种方法包括形成由衬底，第一外延半导体材料和第二外延半导体材料的部分组成的初始鳍结构，形成绝缘材料层，从而过度填充限定 翅片，使一层绝缘材料凹陷，使得最终翅片结构的第二外延半导体部分的一部分（但不是全部）暴露，围绕最终翅片结构形成栅极结构，进一步使绝缘材料层凹陷，使得 第一外延半导体材料被暴露，去除第一外延半导体材料，从而限定下鳍腔，并用受压材料基本上填充底鳍腔。

公开(公告)号：US09209094B2

公开(公告)日：2015-12-08

申请号：US13952993

申请日：2013-07-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L27/00 ,  H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7848

Abstract: A first fin field effect transistor and a second fin field effect transistor are formed on an insulator layer overlying a semiconductor material layer. A first pair of trenches is formed through the insulator layer in regions in which a source region and a drain region of the first fin field effect transistor is to be formed. A second pair of trenches is formed partly into the insulator layer without extending to the top surface of the semiconductor material layer. The source region and the drain region of the first field effect transistor can be epitaxial stressor material portions that are anchored to, and epitaxially aligned to, the semiconductor material layer and apply stress to the channel of the first field effect transistor to enhance performance. The insulator layer provides electrical isolation from the semiconductor material layer to the second field effect transistor.

Abstract translation: 第一鳍状场效应晶体管和第二鳍状场效应晶体管形成在覆盖半导体材料层的绝缘体层上。 在要形成第一鳍式场效应晶体管的源极区域和漏极区域的区域中，通过绝缘体层形成第一对沟槽。 第二对沟槽部分地形成绝缘体层，而不延伸到半导体材料层的顶表面。 第一场效应晶体管的源极区域和漏极区域可以是外延应力材料部分，其被锚定并外延对准半导体材料层，并且将应力施加到第一场效应晶体管的沟道以增强性能。 绝缘体层提供从半导体材料层到第二场效应晶体管的电隔离。

公开(公告)号：US09153498B2

公开(公告)日：2015-10-06

申请号：US13947670

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/823425 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess.

Abstract translation: 本文公开的一种方法包括在替代栅极结构上方的凹槽中形成牺牲蚀刻停止材料，其中牺牲蚀刻停止材料就位，在形成自身之后形成导电耦合到源极/漏极区的自对准接触 执行至少一个处理操作以暴露和去除凹部中的牺牲蚀刻停止材料，从而重新露出凹部，并且在至少再曝光的凹部中形成第三层绝缘材料。

公开(公告)号：US20150263160A1

公开(公告)日：2015-09-17

申请号：US14725505

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L21/823425 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess.

Abstract translation: 本文公开的一种方法包括在替代栅极结构上方的凹槽中形成牺牲蚀刻停止材料，其中牺牲蚀刻停止材料就位，在形成自身之后形成导电耦合到源极/漏极区的自对准接触 执行至少一个处理操作以暴露和去除凹部中的牺牲蚀刻停止材料，从而重新露出凹部，并且在至少再曝光的凹部中形成第三层绝缘材料。

公开(公告)号：US20150102422A1

公开(公告)日：2015-04-16

申请号：US14551606

申请日：2014-11-24

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/28 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，集成电路包括半导体衬底。 第一翅片和第二翅片彼此相邻，从半导体衬底延伸。 第一翅片具有第一上部，第二翅片具有第二上部。 第一外延部分覆盖第一上部，第二外延部分覆盖第二上部。 第一硅化物层覆盖第一外延部分，第二硅化物层覆盖第二外延部分。 第一和第二硅化物层彼此间隔开以限定横向间隙。 电介质隔离物由电介质材料形成并横跨横向间隙。 接触形成材料覆盖介质间隔物和第一和第二硅化物层的在电介质间隔物的横向上方的部分。

公开(公告)号：US08941156B2

公开(公告)日：2015-01-27

申请号：US13735315

申请日：2013-01-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US08921191B2

公开(公告)日：2014-12-30

申请号：US13759156

申请日：2013-02-05

Applicant: GlobalFoundries, Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7853 ,  H01L21/28 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，集成电路包括半导体衬底。 第一翅片和第二翅片彼此相邻，从半导体衬底延伸。 第一翅片具有第一上部，第二翅片具有第二上部。 第一外延部分覆盖第一上部，第二外延部分覆盖第二上部。 第一硅化物层覆盖第一外延部分，第二硅化物层覆盖第二外延部分。 第一和第二硅化物层彼此间隔开以限定横向间隙。 电介质隔离物由电介质材料形成并横跨横向间隙。 接触形成材料覆盖介质间隔物和第一和第二硅化物层的在电介质间隔物的横向上方的部分。