公开(公告)号：US09590074B1

公开(公告)日：2017-03-07

申请号：US14960380

申请日：2015-12-05

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/311 ,  H01L27/11 ,  H01L21/027 ,  H01L21/822 ,  H01L29/78 ,  H01L21/304 ,  H01L21/324

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The method for preventing epitaxial growth in a semiconductor device begins with patterning a photoresist layer over a semiconductor structure having a set of fin ends on a set of fins of a FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step. In another aspect of the invention, a semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends.

Abstract translation: 用于防止半导体器件中的外延生长的方法开始于在FinFET结构的一组鳍片上具有一组翅片端的半导体结构上的光致抗蚀剂层图案化。 翅片组通过第一介电材料彼此隔离。 光致抗蚀剂被图案化在鳍片端部上，使得其与FinFET结构的其它区域上的光致抗蚀剂图案不同。 使用光致抗蚀剂图案在一组翅片端部上形成一组介质块。 所述介电块组在随后的外延生长步骤中防止在所述鳍片端部的外延生长。 在本发明的另一方面，一种半导体器件包括一组翅片结构，其鳍片结构的相应垂直表面具有一组翅片端，并且由一组沟槽与其它翅片结构隔开。 每个翅片结构具有比该组沟槽中的电介质材料的顶表面高的顶表面。 一组介电块设置在翅片端部的集合处，所述介电块具有与翅片结构的顶表面上或上方的顶表面水平，所述顶部表面限制在翅片端部处的过度的外延生长。

公开(公告)号：US09583479B1

公开(公告)日：2017-02-28

申请号：US14995324

申请日：2016-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L29/94 ,  H01L27/02 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0222 ,  G11C5/145 ,  H01L21/31105 ,  H01L21/823431 ,  H01L28/40 ,  H01L29/66181 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H02M3/07 ,  H02M3/073 ,  H02M2003/076

Abstract: A charge pump for an integrated circuit includes a substrate, first and second transistors and a capacitor. The first transistor includes first source and first drain regions disposed within the substrate and defining a first channel therebetween. The first source and first drain regions are implanted with one of an n-type and a p-type dopant. The second transistor includes second source and second drain regions disposed within the substrate and defining a second channel therebetween. The second source and second drain regions implanted with the same type dopant as the first source region. The capacitor includes a metal terminal and a substrate terminal with a dielectric therebetween. The substrate terminal is disposed within the substrate and implanted with the same type dopant as the first source region. The substrate terminal contacts the first drain region and second source region within the substrate to provide electrical continuity therebetween.

Abstract translation: 集成电路的电荷泵包括衬底，第一和第二晶体管和电容器。 第一晶体管包括设置在衬底内并且在其间限定第一通道的第一源极和第一漏极区域。 第一源极和第一漏极区域注入n型和p型掺杂物中的一种。 第二晶体管包括设置在衬底内并在其间限定第二通道的第二源极和第二漏极区域。 第二源极和第二漏极区域注入与第一源极区域相同类型的掺杂剂。 该电容器包括金属端子和其间具有电介质的衬底端子。 衬底端子设置在衬底内并且注入与第一源区相同类型的掺杂剂。 衬底端子接触衬底内的第一漏极区域和第二源极区域，以在它们之间提供电连续性。

公开(公告)号：US09543298B1

公开(公告)日：2017-01-10

申请号：US15067455

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0273 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method of forming a single diffusion break includes etching rows of fins into a substrate of a structure from a patterned fin hardmask, the remaining fin hardmask being self-aligned with the fins. A first dielectric fill material is disposed and planarized over the structure to expose the fin hardmask. A photoresist layer is disposed over the structure. An isolation region is patterned across the fins to form first and second parallel fin arrays, wherein any remaining photoresist layer has self-aligned edges which are self-aligned with the isolation region. The self-aligned edges are trimmed to expose end portions of the fin hardmask. The exposed end portions are removed. The remaining photoresist layer is removed. A second dielectric fill material is disposed and planarized over the structure to form a base for a single diffusion break (SDB) in the isolation region.

Abstract translation: 形成单个扩散断裂的方法包括从图案化散热片硬掩模将排成一排散热片蚀刻成结构的基板，剩余的散热片硬掩模与散热片自对准。 在结构上设置和平坦化第一介电填充材料以暴露散热片硬掩模。 光致抗蚀剂层设置在结构上。 隔离区跨越翅片形成图案以形成第一和第二平行翅片阵列，其中任何残留的光致抗蚀剂层具有与隔离区自对准的自对准边缘。 自对准边缘被修剪以暴露散热片硬掩模的端部。 露出的端部被去除。 去除剩余的光致抗蚀剂层。 第二介电填充材料在结构上设置和平坦化，以形成隔离区域中的单个扩散断裂（SDB）的基底。

公开(公告)号：US09443931B2

公开(公告)日：2016-09-13

申请号：US14988050

申请日：2016-01-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Guillaume Bouche ,  Gabriel Padron Wells

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L21/311 ,  H01L21/308 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

公开(公告)号：US09431303B2

公开(公告)日：2016-08-30

申请号：US14516674

申请日：2014-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L21/285 ,  H01L21/321

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/28531 ,  H01L21/28568 ,  H01L21/321 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/45

Abstract: Contact liners for integrated circuits and fabrication methods thereof are presented. The methods include: fabricating an integrated circuit structure having a first transistor having at least one of a p-type source region or a p-type drain region and a second transistor having at least one of an n-type source region or an n-type drain region, and the fabricating including: forming a contact liner at least partially over both the first transistor and the second transistor, the contact liner including a first contact liner material and a second contact liner material, wherein the first contact liner material is selected to facilitate electrical connection to the at least one p-type source region or p-type drain region of the first transistor, and the second contact liner material is selected to facilitate electrical connection to the at least one n-type source region or n-type drain region of the second transistor.

Abstract translation: 介绍了集成电路的接触衬垫及其制造方法。 所述方法包括：制造具有第一晶体管的集成电路结构，所述第一晶体管具有p型源极区或p型漏极区中的至少一个，以及具有n型源区或n型源区中至少一个的第二晶体管， 并且所述制造包括：至少部分地在所述第一晶体管和所述第二晶体管两者上形成接触衬垫，所述接触衬垫包括第一接触衬垫材料和第二接触衬里材料，其中所述第一接触衬里材料被选择 以促进与第一晶体管的至少一个p型源区或p型漏极区的电连接，并且选择第二接触衬垫材料以促进与至少一个n型源区或n型源区的电连接。 型漏极区域。

公开(公告)号：US09331202B2

公开(公告)日：2016-05-03

申请号：US14731876

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract translation: 本文公开的一种说明性方法包括在鳍周围形成翅片保护层，在翅片保护层的一部分上形成牺牲栅电极，形成邻近牺牲栅电极的至少一个侧壁间隔物，去除牺牲栅极 电极，以限定露出所述鳍片保护层的一部分的栅极腔，至少氧化所述鳍片保护层的暴露部分，从而形成所述鳍片保护层的氧化部分，以及去除所述鳍片保护层的氧化部分，从而 从而使得在门腔内的翅片的表面露出。

公开(公告)号：US09276064B1

公开(公告)日：2016-03-01

申请号：US14535433

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guillaume Bouche ,  Gabriel Padron Wells

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L21/311

CPC classification number: H01L29/0673 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

Abstract translation: 提出了用于促进制造堆叠的纳米线，场效应晶体管的方法。 所述方法包括：在栅极结构上形成切割掩模间隔物，栅极结构设置在衬底结构上方的多层上方，栅极结构包括沿其侧壁的侧壁间隔物和覆盖侧壁间隔物的切割掩模间隔物; 通过使用切割掩模间隔物和栅极结构作为掩模切割多个层来限定堆叠结构，并且部分地选择性地蚀刻多个层的至少一个层以部分地掩盖掩模，其中至少一个其它层 通过选择性蚀刻，多层保持未蚀刻; 并且在栅极结构的栅极结构和多个层的上端表面上提供对准掩模间隔物，所述对准掩模间隔物有助于蚀刻多个层的另一层，以选择性地暴露部分端部表面 其他层。

公开(公告)号：US20150340491A1

公开(公告)日：2015-11-26

申请号：US14814183

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hyun-Jin Cho

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

Abstract translation: 提供了替代金属门（RMG）设备中间隔倒角的方法。 具体地，半导体器件设置有由基板形成的一组翅片; 保形地沉积在该组翅片上的硅基层; 形成在硅基层上的蚀刻停止层（例如，氮化钛（TiN）），该蚀刻停止层对于硅，氧化物和氮化物中的至少一个是选择性的; 一组形成在衬底上的RMG结构; 沿着RMG结构集合中的每一个形成的一组隔离物，其中来自该组间隔物中的每一个的垂直材料层被选择性地移除到蚀刻停止层。 通过倒角每个侧壁间隔件，提供了用于后续功函（WF）金属沉积的较宽区域。 同时，每个晶体管沟道区域被蚀刻停止层（例如，TiN）覆盖，其在反应离子蚀刻期间维持原始栅极临界尺寸。

公开(公告)号：US20150325692A1

公开(公告)日：2015-11-12

申请号：US14270833

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for simultaneously providing a set of merged and unmerged fins in a fin field effect transistor device (FinFET) are disclosed. In at least one approach, the FinFET device includes: a set of merged fins and a set of unmerged fins formed from a substrate, the set of unmerged fins adjacent the set of merged fins; and a planar block formed from the substrate, the planar block adjacent one of: the set of merged fins, and the set of unmerged fins. The FinFET device further includes an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins and remains unmerged over the set of unmerged fins. In at least one approach, the set of merged fins and the set of unmerged fins is formed using a sidewall image transfer process.

Abstract translation: 公开了在翅片场效应晶体管器件（FinFET）中同时提供一组合并和非鳍片的方法。 在至少一种方法中，FinFET器件包括：一组合并的散热片和一组从衬底形成的未成形翅片，所述一组未合并的散热片邻近该组合的翅片; 以及由该基板形成的平面块，该平面块相邻于一组合并翅片，以及一组未熔合翼片。 FinFET器件还包括在所述一组合并的散热片中的每一个上的外延材料和所述一组未熔合的翅片中的每一个，其中所述外延材料在所述一组合并的翅片上合并在一起，并且保持未被覆盖在所述一组未熔合的翅片上。 在至少一种方法中，使用侧壁图像转印处理形成所述组合的散热片和所述一组未成形散热片。

公开(公告)号：US20150001627A1

公开(公告)日：2015-01-01

申请号：US13929923

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hyun-Jin Cho

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.