公开(公告)号：US20070120194A1

公开(公告)日：2007-05-31

申请号：US11657592

申请日：2007-01-25

申请人： Masaki Shiraishi ,  Yoshito Nakazawa

发明人： Masaki Shiraishi ,  Yoshito Nakazawa

IPC分类号： H01L29/94

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L24/05 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p− type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p− type semiconductor region is formed under a n+ type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

摘要翻译： 提供了一种降低导通电阻的技术，并且相对于沟槽栅型功率MISFET实现了穿通的防止。 通过形成沟槽，减少输入电容和反馈电容，其中栅电极形成为具有大约1μm或更小的深度的深度，形成至 深度以便不覆盖凹槽的底部，并且在+ SUP +型半导体区域形成杂质浓度高于p +型半导体区域的p型半导体区域 半导体区域用作沟槽栅型功率MISFET的源极区域，使得p型半导体区域用作沟槽栅型功率MISFET的穿通阻挡层。

公开(公告)号：US20050037579A1

公开(公告)日：2005-02-17

申请号：US10948262

申请日：2004-09-24

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US06803281B2

公开(公告)日：2004-10-12

申请号：US10785103

申请日：2004-02-25

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

公开(公告)号：US06720220B2

公开(公告)日：2004-04-13

申请号：US10325915

申请日：2002-12-23

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US08587087B2

公开(公告)日：2013-11-19

申请号：US13060737

申请日：2010-02-25

申请人： Daisuke Arai ,  Yoshito Nakazawa ,  Norio Hosoya

发明人： Daisuke Arai ,  Yoshito Nakazawa ,  Norio Hosoya

IPC分类号： H01L29/74

CPC分类号： H01L29/7395 ,  H01L24/05 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66333 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/00

摘要： In order to improve characteristics of an IGBT, particularly, to reduce steady loss, turn-off time and turn-off loss, a thickness of a surface semiconductor layer is set to about 20 nm to 100 nm in an IGBT including: a base layer; a buried insulating film provided with an opening part; the surface semiconductor layer connected to the base layer below the opening part; a p type channel forming layer formed in the surface semiconductor layer; an n+ type source layer; a p+ type emitter layer; a gate electrode formed over the surface semiconductor layer via a gate insulating film; an n+ type buffer layer; and a p type collector layer.

摘要翻译： 为了改善IGBT的特性，特别是为了减少稳定损耗，关断时间和关断损耗，在包括基底层的IGBT中，表面半导体层的厚度设定为约20nm至100nm ; 设置有开口部的埋入绝缘膜; 所述表面半导体层在所述开口部的下方与所述基底层连接; 形成在所述表面半导体层中的p型沟道形成层; n +型源层; p +型发射极层; 栅电极，经由栅极绝缘膜形成在所述表面半导体层上; n +型缓冲层; 和p型集电体层。

公开(公告)号：US08441065B2

公开(公告)日：2013-05-14

申请号：US12851101

申请日：2010-08-05

申请人： Hirokatsu Suzuki ,  Atsushi Fujiki ,  Yoshito Nakazawa

发明人： Hirokatsu Suzuki ,  Atsushi Fujiki ,  Yoshito Nakazawa

IPC分类号： H01L29/76

CPC分类号： H01L29/66666 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823487 ,  H01L27/0248 ,  H01L27/088 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7835

摘要： A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps.

摘要翻译： 提供了组合可靠性和电气特性保证的半导体器件。 提供了形成在同一半导体衬底上的功率MOSFET和保护电路。 功率MOSFET是沟槽栅极垂直型P沟道MOSFET，并且栅极电极的导通类型被假定为P型。 保护电路包括平面栅极水平型偏移P沟道MOSFET，并且假定栅极电极的导电类型为N型。 这些栅电极和栅电极分开形成。

公开(公告)号：US20110309437A1

公开(公告)日：2011-12-22

申请号：US13214131

申请日：2011-08-19

申请人： NOBUYUKI SHIRAI ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

发明人： NOBUYUKI SHIRAI ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L27/088

CPC分类号： H01L29/7806 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/20 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7823 ,  H01L29/872 ,  H01L29/8725

摘要： To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contact region for contact with the metal, the metal being electrically connected to the second semiconductor region, and a center-to-center distance between adjacent first conductors in the first region being smaller than that between adjacent second conductors in the second region.

公开(公告)号：US08008714B2

公开(公告)日：2011-08-30

申请号：US12901929

申请日：2010-10-11

申请人： Nobuyuki Shirai ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

发明人： Nobuyuki Shirai ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L29/76

CPC分类号： H01L29/7806 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/20 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7823 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device, including a MOSFET, has a plurality of transistor cell regions disposed in a semiconductor substrate. A source electrode of the MOSFET is disposed over a main surface of the semiconductor substrate and is in contact with a top surface of a source region in each of the plurality of transistor cell regions. A drain electrode of the MOSFET is a disposed over a back surface of the semiconductor substrate and is electrically connected to the semiconductor substrate. A Schottky cell region is disposed between the plurality of transistor cell regions in the semiconductor substrate. The source electrode is in contact with a part of the main surface of the semiconductor so as to form a Schottky junction in the Schottky cell region.

摘要翻译： 包括MOSFET的半导体器件具有设置在半导体衬底中的多个晶体管单元区域。 MOSFET的源极设置在半导体衬底的主表面上，并且与多个晶体管单元区域中的每一个中的源极区的顶表面接触。 MOSFET的漏电极设置在半导体衬底的背面上并与半导体衬底电连接。 肖特基电池区设置在半导体衬底中的多个晶体管单元区域之间。 源电极与半导体的主表面的一部分接触，以便在肖特基电池区域中形成肖特基结。

公开(公告)号：US20110115033A1

公开(公告)日：2011-05-19

申请号：US12949765

申请日：2010-11-18

申请人： Tomohiro Tamaki ,  Yoshito Nakazawa ,  Satoshi Eguchi

发明人： Tomohiro Tamaki ,  Yoshito Nakazawa ,  Satoshi Eguchi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

摘要： A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

摘要翻译： 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。

公开(公告)号：US07829946B2

公开(公告)日：2010-11-09

申请号：US12404285

申请日：2009-03-14

申请人： Nobuyuki Shirai ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

发明人： Nobuyuki Shirai ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L29/76

CPC分类号： H01L29/7806 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/20 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7823 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device including a MOSFET has a plurality of transistor cell regions disposed on a semiconductor substrate and a Schottky cell region disposed between the plurality of transistor cell regions. Each transistor cell region has a plurality of first trenches disposed in a main surface of the semiconductor substrate, a well region between the plurality of first trenches, a first gate insulating film and a first gate electrode of the MOSFET in each first trench, and a source region of the MOSFET in each well region. The Schottky cell region has a plurality of second trenches disposed in the main surface of the semiconductor substrate, a second gate insulating film and a second gate electrode of the MOSFET in each second trench, gate lead-out wiring connected to each second gate electrode, and a plurality of guard ring regions enclosing the respective second trenches.

摘要翻译： 包括MOSFET的半导体器件具有设置在半导体衬底上的多个晶体管单元区域和设置在多个晶体管单元区域之间的肖特基电池区域。 每个晶体管单元区域具有设置在半导体衬底的主表面中的多个第一沟槽，多个第一沟槽中的阱区，第一栅极绝缘膜和第一沟槽中的MOSFET的第一栅电极，以及 在每个阱区域中的MOSFET的源极区域。 所述肖特基电池区域具有设置在所述半导体衬底的主表面中的多个第二沟槽，在每个第二沟槽中的所述MOSFET的第二栅极绝缘膜和第二栅电极，连接到每个第二栅电极的栅极引出布线， 以及包围各个第二沟槽的多个保护环区域。