公开(公告)号：US20050145987A1

公开(公告)日：2005-07-07

申请号：US11013514

申请日：2004-12-17

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L29/76

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US06734814B2

公开(公告)日：2004-05-11

申请号：US10167460

申请日：2002-06-14

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M7/3006 ,  H03M3/368 ,  H03M3/418 ,  H03M3/43 ,  H03M3/45 ,  H03M3/452 ,  H03M7/3022 ,  H03M7/3028 ,  H03M7/3033 ,  H03M7/3037

摘要： In a modulator, an attenuator attenuates an input signal, a delay element gives a delay of 1 sample period to the attenuated signal, an adder subtracts a quantized signal that has been fed back with a delay of 1 sample period, from the delayed signal, two or more integrators integrate a result of the subtraction, an adder which adds outputs of the respective integrators and the attenuated signal, and a quantizer quantizes a result of the addition, outputs a result of the quantization as an output signal and feeds back the output signal to the subtractor.

摘要翻译： 在调制器中，衰减器衰减输入信号，延迟元件给衰减信号提供1个采样周期的延迟，加法器从延迟信号中减去已经以1个采样周期的延迟反馈的量化信号， 两个或更多个积分器集成减法的结果，加上各积分器的输出的加法器和衰减的信号，量化器对加法的结果进行量化，输出量化的结果作为输出信号，反馈输出 发信号给减法器。

公开(公告)号：US06323794B1

公开(公告)日：2001-11-27

申请号：US09437405

申请日：1999-11-10

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M7/3022 ,  H03M3/414 ,  H03M3/458 ,  H03M3/50

摘要： Modulators (M1 to Mk (k≧2)) are connected in a multi-stage such that each of quantization errors (e1, e2, . . . ) of the modulators (M1 to Mk−1) is fed to the input of the next stage modulator. Each output signal of the modulators (M2 to Mk) is fed back to the input of the immediately preceding modulator. The modulators (M1 to Mk) are all first-order modulators. Only the final stage modulator (Mk) has a multi-bit quantizer (6), and all the preceding modulators (M1 to Mk−1) have an 1-bit quantizer (3). Accordingly, a noise-shaping equal to that of a multi-bit higher-order modulator is realized on a small-scale circuit while retaining stability.

摘要翻译： 调制器（M1至Mk（k> = 2））以多级连接，使得调制器（M1至Mk-1）的每个量化误差（e1，e2，...）被馈送到 下一级调制器。 调制器（M2至Mk）的每个输出信号被反馈到紧接在前的调制器的输入端。 调制器（M1至Mk）都是一阶调制器。 只有最后级调制器（Mk）具有多位量化器（6），并且所有先前的调制器（M1至Mk-1）都具有1位量化器（3）。 因此，在保持稳定性的同时，在小规模电路上实现等于多位高阶调制器的噪声整形。

公开(公告)号：US06300890B1

公开(公告)日：2001-10-09

申请号：US09716241

申请日：2000-11-21

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M3/46

摘要： A delta-sigma modulator comprises a 1-bit quantizer located for quantizing an analog signal applied thereto, and for outputting a first quantized digital signal, a 1-bit DA converter converting the first quantized digital signal into a quantized analog signal, a subtracting circuit for subtracting the quantized analog signal output from the 1-bit DA converter from the analog signal input to the 1-bit quantizer, and an input integrating circuit series including a series of one or more stages each of which includes a subtracter and an integrator for integrating an output of the subtracter, one subtracter at a first stage subtracting the quantized analog signal delayed by a delay element from an input analog signal input to the delta-sigma modulator, and one integrator at a final stage outputting its output to the 1-bit quantizer. A multiple-bit quantizer quantizes an analog output of the subtracting circuit and outputs a second quantized digital signal. A differentiator then calculates an Nth-order derivative of the second quantized digital signal from the multiple-bit quantizer, N being equal to a number of the one or more stages included in the input integrating circuit series, and an adder adds an output of the differentiator to the first quantized digital signal from the 1-bit quantizer.

摘要翻译： Δ-Σ调制器包括1位量化器，用于量化施加到其上的模拟信号，并用于输出第一量化数字信号，将第一量化数字信号转换为量化模拟信号的1位DA转换器，减法电路 用于从输入到1位量化器的模拟信号中减去从1位DA转换器输出的量化模拟信号，以及包括一系列一级或多级的输入积分电路系列，每级包括减法器和积分器 对减法器的输出进行积分，一个减法器在第一级从输入到Δ-Σ调制器的输入模拟信号中减去由延迟元件延迟的量化模拟信号，以及一个积分器，将其输出输出到1- 位量化器。 多位量化器量化减法电路的模拟输出并输出第二量化数字信号。 然后，微分器计算来自多位量化器的第二量化数字信号的N次导数，N等于包括在输入积分电路序列中的一个或多个级的数，并且加法器将 与1位量化器的第一个量化数字信号进行微分。

公开(公告)号：US06232804B1

公开(公告)日：2001-05-15

申请号：US09413751

申请日：1999-10-06

申请人： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

发明人： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

IPC分类号： G11C2702

CPC分类号： G11C27/026

摘要： In a sample hold circuit (6, 50, 60) capable of relaxing a dependency of a voltage of an analogue input signal on an ON resistance of a switch (2). In the sample hold circuit (6, 50, 60), plural reference voltages VrefN are supplied, and unit switches (11e) forming the switch (2) are selectively activated (an ON state) based on a comparison results (whether or not the voltage of the analogue input signal is greater than each reference voltage) from plural comparison circuits (13e) whose operations are performed based on the voltage of the analogue input signal (1).

摘要翻译： 在能够放松模拟输入信号的电压对开关（2）的导通电阻的依赖性的采样保持电路（6,50,60）中。 在采样保持电路（6,50,60）中，提供多个参考电压VrefN，并且基于比较结果（形成开关（2））的单元开关（11e）是否被选择性地激活（ON状态） 根据模拟输入信号（1）的电压执行其操作的多个比较电路（13e），模拟输入信号的电压大于每个参考电压）。

公开(公告)号：US5995031A

公开(公告)日：1999-11-30

申请号：US968207

申请日：1997-11-12

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0663 ,  H03M1/747 ,  H03M3/464 ,  H03M3/502

摘要： A multi-bit D/A converter which improves the linearity of an analog output relative to a digital input is provided. A switch control circuit (1) turns on D some of a plurality of switches (S1 to SM) which are arranged in ascending order starting with a switch determined by a start position determination circuit (3) and turns off the remaining switches, the number of switches turned on being dependent on a digital signal (DIG). The start position determination circuit (3) sequentially changes the switches (S1, S3, S5, . . . ) serving as a selection start position to determine the selection start position for each input of the digital signal (DIG) provided in synchronism with a clock signal (CLK).

摘要翻译： 提供了一种提高模拟输出相对于数字输入的线性度的多位D / A转换器。 开关控制电路（1）接通D开始的开关位置确定电路（3）确定的开关的升序排列的多个开关（S1至SM）中的一些，并且关闭其余的开关 开关依赖于数字信号（DIG）。 开始位置确定电路（3）顺序地改变用作选择开始位置的开关（S1，S3，S5 ...），以确定与设置的与数字信号（DIG）同步的数字信号（DIG）的每个输入的选择开始位置 时钟信号（CLK）。

公开(公告)号：US5731776A

公开(公告)日：1998-03-24

申请号：US714423

申请日：1996-09-16

申请人： Toshio Kumamoto ,  Osamu Matsumoto

发明人： Toshio Kumamoto ,  Osamu Matsumoto

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/362

摘要： A ladder resistance (1) consisting of resistance elements (r1, r2, . . . , r8) connected in series with intermediate taps (T1, T2, . . . , T7) interposed is so arranged as to be folded back at its midpoint. Pairs of differential comparators (C1 and C7, C2 and C6, . . . ) which are connected to common intermediate taps are each disposed adjacently so as to be nearest to the intermediate tap to be connected thereto. Accordingly, wires connecting the differential comparators (C1, C2, . . . , C7) to the intermediate taps (T1, T2, . . . , T7) become shorter and an area of a semiconductor chip needed for arranging the wires can be reduced. Thus, reduction in area of the semiconductor chip needed for providing the device therein is achieved.

摘要翻译： 插入与中间抽头（T1，T2，...，T7）串联连接的电阻元件（r1，r2，...，r8）组成的梯形电阻（1）被布置为在其中点 。 连接到公共中间抽头的差分比较器（C1和C7，C2和C6，...）的对相邻设置成最靠近要与其连接的中间抽头。 因此，将差分比较器（C1，C2，... C7）连接到中间抽头（T1，T2，...，T7）的电线变短，并且可以减少布线所需的半导体芯片的面积 。 因此，实现了在其中提供设备所需的半导体芯片的面积减小。

公开(公告)号：US5629700A

公开(公告)日：1997-05-13

申请号：US552016

申请日：1995-11-02

申请人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/44 ,  H03M1/34

CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/069 ,  H03M1/1215 ,  H03M1/167

摘要： An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.

摘要翻译： A / D转换器模块A / D1将模拟输入信号Vin转换为数字信号并输出​​其D / A输出。 第一SH / SUBT7,8以与所述A / D转换相同的定时采样信号Vin和电压VRM，并分别输出相应采样值和保持期间的D / A输出的结果。 减法的结果都是几十mV，不需要考虑差分放大器DIFF11的线性度。 在采样期间，电路SHR1输出从A / D转换器模块A / D1中的梯形电阻器的特定2点取出的每个参考分接电压与电压VRM之间的差分电压，而差分放大器DIFF12施加参考 电压到下一个A / D转换器模块A / D2。 这样的操作在每个阶段进行。 因此，可以使得在第一级中具有优异线性度的任何S / H电路和放大器不必减少电力消耗。

公开(公告)号：US5469047A

公开(公告)日：1995-11-21

申请号：US311433

申请日：1994-09-26

申请人： Toshio Kumamoto ,  Takahiro Miki ,  Hiroyuki Kouno

发明人： Toshio Kumamoto ,  Takahiro Miki ,  Hiroyuki Kouno

IPC分类号： G05F3/16 ,  G05F3/20

CPC分类号： G05F3/20

摘要： In order to obtain a constant current circuit which has an excellent constant current property and requires no plural bias circuits, a base of an NPN bipolar transistor (5) and a gate of an N-channel MOS transistor (6) are connected to a first terminal (1) in common. A collector of the transistor (5) is connected to a second terminal (2) and a source of a transistor (6) is connected to a third terminal respectively, while a voltage source (59) is connected between the first and third terminals. An emitter of the transistor (5) is connected with a drain of the transistor (6). Identical bias voltages are supplied to the base and the gate, while a gate-to-drain voltage of the transistor (6) is equal to a base-to-emitter voltage of the transistor (5). Thus, the transistor (6) operates in a pentode region, to serve as a constant current load for the transistor (5).

摘要翻译： 为了获得具有优异的恒定电流特性并且不需要多个偏置电路的恒流电路，NPN双极晶体管（5）的基极和N沟道MOS晶体管（6）的栅极连接到第一 终端（1）共同点。 晶体管（5）的集电极连接到第二端子（2），并且晶体管（6）的源极分别连接到第三端子，而电压源（59）连接在第一和第三端子之间。 晶体管（5）的发射极与晶体管（6）的漏极连接。 相同的偏置电压被提供给基极和栅极，而晶体管（6）的栅极 - 漏极电压等于晶体管（5）的基极 - 发射极电压。 因此，晶体管（6）工作在五极管区域，用作晶体管（5）的恒定电流负载。

公开(公告)号：US5341037A

公开(公告)日：1994-08-23

申请号：US886904

申请日：1992-05-22

申请人： Takahiro Miki ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Toshio Kumamoto

IPC分类号： G11C27/02 ,  H03K5/159

CPC分类号： G11C27/026 ,  G11C27/024

摘要： Positive and negative output ends of a differential circuit in a sample hold circuit are connected to capacitors through switch circuits. Further, collectors of two input transistors of a buffer circuit connected to the sample hold circuit are driven by a collector driving differential circuit, so as to make the collector.multidot.base voltages of two input transistors same to each other. Consequently, a stable sample hold circuit having an arbitrary gain can be provided. In addition, drifts of outputs from two capacitors in the sample hold circuit can be made equal to each other by the buffer circuit.

摘要翻译： 采样保持电路中的差分电路的正和负输出端通过开关电路连接到电容器。 此外，连接到采样保持电路的缓冲电路的两个输入晶体管的集电极由集电极驱动差分电路驱动，以使两个输入晶体管的集电极基极彼此相同。 因此，可以提供具有任意增益的稳定的采样保持电路。 此外，可以通过缓冲电路将采样保持电路中的两个电容器的输出漂移相互相等。