公开(公告)号：US20190027536A1

公开(公告)日：2019-01-24

申请号：US15767127

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  Kaan Oguz ,  Kevin P. O'Brien ,  Tofizur Rahman ,  Brian S. Doyle ,  Tahir Ghani ,  Mark L. Doczy

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Disclosed herein are electrical contacts for magnetoresistive random access memory (MRAM) devices and related memory structures, devices, and methods. For example, and electrical contact for an MRAM device may include: a tantalum region; a barrier region formed of a first material; and a passivation region formed of a second material and disposed between the tantalum region and the barrier region, wherein the second material includes tantalum nitride and is different from the first material.

公开(公告)号：US20180182952A1

公开(公告)日：2018-06-28

申请号：US15735395

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Daniel R. Lamborn ,  Oleg Golonzka ,  Christopher J. Wiegand ,  Philip E. Heil ,  MD Tofizur Rahman ,  Rebecca J. Castellano ,  Tarun Bansal

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between fixed and free layers; a dielectric film directly contacting sidewalls of the first electrode; and a metallic layer coupled to the side-walls via the dielectric film; wherein (a) a vertical axis intersects the first and second electrodes and the MTJ but not the metallic layer, (b) a first horizontal axis intersects the metallic layer, the dielectric film, and the first electrode; and (c) a second horizontal axis, between the first horizontal axis and the MTJ, intersects the dielectric film and the first electrode but not the capping layer. Other embodiments are described herein.

公开(公告)号：US09559060B2

公开(公告)日：2017-01-31

申请号：US15220270

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L21/70 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/08 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源/漏接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的ILD内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：US20160336271A1

公开(公告)日：2016-11-17

申请号：US15220270

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/8234 ,  H01L29/08 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20160126191A1

公开(公告)日：2016-05-05

申请号：US14994109

申请日：2016-01-12

Applicant: Intel Corporation

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/08 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源/漏接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的ILD内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：US20150188033A1

公开(公告)日：2015-07-02

申请号：US14140758

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Daniel R. LAMBORN ,  Oleg Golonzka ,  Christopher Wiegand

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08

CPC classification number: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods of forming a memory device structure are described. Those methods may include forming a non-conductive spacer material on a top electrode of a magnetic tunnel junction structure, and then forming a highly selective material on the non-conductive spacer material of the magnetic tunnel junction prior to etching a bottom electrode of the magnetic tunnel junction.

Abstract translation: 描述形成存储器件结构的方法。 这些方法可以包括在磁性隧道结结构的顶部电极上形成非导电间隔物材料，然后在蚀刻磁性体的底部电极之前在磁性隧道结的非导电间隔物材料上形成高选择性材料 隧道交界处。

公开(公告)号：US12142566B2

公开(公告)日：2024-11-12

申请号：US18206539

申请日：2023-06-06

Applicant: Intel Corporation

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20240290788A1

公开(公告)日：2024-08-29

申请号：US18175591

申请日：2023-02-28

Applicant: Intel Corporation

Inventor： Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Robin Chao ,  David Towner ,  Orb Acton ,  Omair Saadat ,  Feng Zhang ,  Dax M. Crum ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka ,  Anand S. Murthy

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.

公开(公告)号：US11908856B2

公开(公告)日：2024-02-20

申请号：US16719257

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US11621395B2

公开(公告)日：2023-04-04

申请号：US16396465

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.