公开(公告)号：US20180151420A1

公开(公告)日：2018-05-31

申请号：US15878546

申请日：2018-01-24

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Terry A. Spooner ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76825 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.

公开(公告)号：US09899317B1

公开(公告)日：2018-02-20

申请号：US15279775

申请日：2016-09-29

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wei Wang ,  Chi-Chao Yang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3065

CPC classification number: H01L23/5226 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295

Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.

公开(公告)号：US09786603B1

公开(公告)日：2017-10-10

申请号：US15272883

申请日：2016-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Terry A. Spooner ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: Conductive contacts and methods of forming vias include forming a trench that penetrates a dielectric layer to expose a surface of an underlying conductor. Exposed surfaces of the dielectric layer and the exposed surface of the underlying conductor are nitridized to form a layer of nitridation at the exposed surfaces. The exposed surface of the underlying conductor is etched away to form a recessed area in the underlying conductor. A conductive via is formed in the trench and the recessed area that forms a conductive contact with the underlying conductor.

公开(公告)号：US09786550B2

公开(公告)日：2017-10-10

申请号：US14749811

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： Stephen M. Gates ,  Gregory M. Fritz ,  Eric A. Joseph ,  Terry A. Spooner

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76814 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76888 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53266

Abstract: A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact.

公开(公告)号：US20170263557A1

公开(公告)日：2017-09-14

申请号：US15069439

申请日：2016-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Baozhen Li ,  Kirk D. Peterson ,  Terry A. Spooner ,  Junli Wang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/28562 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dieletric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

公开(公告)号：US20170117177A1

公开(公告)日：2017-04-27

申请号：US15396961

申请日：2017-01-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Terry A. Spooner ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/033

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

公开(公告)号：US20170098577A1

公开(公告)日：2017-04-06

申请号：US14872302

申请日：2015-10-01

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Baozhen Li ,  Kirk D. Peterson ,  John E. Sheets, II ,  Terry A. Spooner

IPC: H01L21/768 ,  H01L21/66 ,  G06F17/50

CPC classification number: H01L21/76892 ,  G06F17/5036 ,  G06F17/5063 ,  G06F17/5072 ,  G06F17/5081 ,  H01L22/20

Abstract: A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.

公开(公告)号：US20170004996A1

公开(公告)日：2017-01-05

申请号：US14755647

申请日：2015-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Terry A. Spooner ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract translation: 一种形成通孔的方法，其包括在层叠介电层上存在的硬掩模层上的多个心轴上形成侧壁间隔物。 使用侧壁间隔件和多个心轴的一部分来蚀刻硬掩模层以形成硬掩模材料的第一支柱。 使用硬掩模材料的第一柱作为掩模蚀刻层间电介质层以限定第一通孔。 多个心轴被移除。 使用间隔物蚀刻硬掩模层以限定硬掩模材料的第二支柱。 使用硬掩模材料的第二柱蚀刻层间电介质层以提供第二通孔。

公开(公告)号：US09490168B1

公开(公告)日：2016-11-08

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US20150289361A1

公开(公告)日：2015-10-08

申请号：US14739703

申请日：2015-06-15

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

Abstract translation: 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。