公开(公告)号：US20160372599A1

公开(公告)日：2016-12-22

申请号：US15246468

申请日：2016-08-24

Applicant: Intel Corporation

Inventor： Jacob JENSEN ,  Tahir GHANI ,  Mark Y. LIU ,  Harold KENNEL ,  Robert JAMES

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/268 ,  H01L21/324 ,  H01L21/265 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

Abstract translation: 一种非平面晶体管，其包括设置在半导体鳍片的相对端上的部分熔融的凸起半导体源极/漏极，其间设置有栅极堆叠。 升高的半导体源极/漏极包括在熔体深度之上的超激活掺杂剂区域和低于熔体深度的活化掺杂剂区域。 超活化掺杂剂区域具有比活化的掺杂剂区域更高的活化掺杂剂浓度和/或具有在整个熔融区域中恒定的活化的掺杂剂浓度。 翅片形成在基板上，并且半导体材料或半导体材料堆叠沉积在设置在沟道区域的相对侧上的翅片的区域上以形成升高的源极/漏极。 进行脉冲激光退火以仅将融化的半导体材料的一部分熔化在熔体深度之上。

公开(公告)号：US20240429238A1

公开(公告)日：2024-12-26

申请号：US18825952

申请日：2024-09-05

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  Omair SAADAT ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

公开(公告)号：US20240363628A1

公开(公告)日：2024-10-31

申请号：US18767458

申请日：2024-07-09

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20240284652A1

公开(公告)日：2024-08-22

申请号：US18644874

申请日：2024-04-24

Applicant: Intel Corporation

Inventor： Peng ZHENG ,  Varun MISHRA ,  Tahir GHANI

IPC: H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US20240222276A1

公开(公告)日：2024-07-04

申请号：US18089877

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H05K1/18

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H05K1/181 ,  H05K2201/10159

Abstract: Structures having lookup table decoders for FPGAs with high DRAM transistor density are described. In an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. A plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.

公开(公告)号：US20240221821A1

公开(公告)日：2024-07-04

申请号：US18089886

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC: G11C11/409 ,  H01L23/522 ,  H01L23/528

CPC classification number: G11C11/409 ,  H01L23/5226 ,  H01L23/5283

Abstract: Structures having two-transistor gain cell are described. In an example, an integrated circuit structure includes a frontend device layer including a read transistor. A backend device layer is above the frontend device layer, the backend device layer including a write transistor. An intervening interconnect layer is between the backend device layer and the frontend device layer, the intervening interconnect layer coupling the write transistor of the backend device layer to the read transistor of the front-end device layer.

公开(公告)号：US20240120335A1

公开(公告)日：2024-04-11

申请号：US18390952

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Biswajeet GUHA ,  William HSU ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

公开(公告)号：US20240113116A1

公开(公告)日：2024-04-04

申请号：US17958293

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  YenTing CHIU ,  Tahir GHANI ,  Leonard P. GULER ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Anand S. MURTHY ,  Wonil CHUNG ,  Allen B. GARDINER

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/775

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. Other embodiments may be described and/or claimed.

公开(公告)号：US20240105599A1

公开(公告)日：2024-03-28

申请号：US17955511

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vishal TIWARI ,  Tahir GHANI ,  Mohit K. HARAN ,  Desalegne B. TEWELDEBRHAN

IPC: H01L23/528 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L29/4232

Abstract: Mushroomed via structures for trench contact or gate contact are described. In an example, an integrated circuit structure includes a trench contact structure over an epitaxial source or drain structure. A dielectric layer is over the trench contact structure. A trench contact via is in an opening in the dielectric layer, the trench contact via in contact with the trench contact structure. A trench contact via extension is on the trench contact via. The trench contact via extension above the dielectric layer and extending laterally beyond the trench contact via.

公开(公告)号：US20240030348A1

公开(公告)日：2024-01-25

申请号：US18374959

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/02603 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/42392 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.