公开(公告)号：US10008565B2

公开(公告)日：2018-06-26

申请号：US15626018

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/786 ,  H01L29/36 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L21/3065 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/167 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

公开(公告)号：US09859278B2

公开(公告)日：2018-01-02

申请号：US15037618

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Robert S. Chau

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/423 ,  H01L29/786 ,  H01L29/267

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/78669 ,  H01L29/78684

Abstract: An apparatus including a complimentary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET); and a p-channel MOSFET, wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is subject to a bi-axial tensile strain. A method including forming an n-channel metal oxide semiconductor field effect transistor (MOSFET); forming a p-channel MOSFET; and connecting the gate electrodes and the drain regions of the n-channel MOSFET and the p-channel MOSFET, wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain.

公开(公告)号：US09812574B2

公开(公告)日：2017-11-07

申请号：US14938739

申请日：2015-11-11

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  G11C11/412 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/785 ,  G11C11/412 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US09786786B2

公开(公告)日：2017-10-10

申请号：US15345546

申请日：2016-11-08

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert S. Chau

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/267 ,  H01L29/165 ,  H01L29/10 ,  H01L29/15 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/12 ,  H01L29/51

CPC classification number: H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/151 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20170229543A1

公开(公告)日：2017-08-10

申请号：US15504280

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/10 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Transistor devices having indium gallium arsenide active channels, and processes for the fabrication of the same, that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium gallium arsenide material may be deposited in narrow trenches which may result in a fin that has indium rich surfaces and a gallium rich central portion. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous composition indium gallium arsenide active channels.

公开(公告)号：US20170194506A1

公开(公告)日：2017-07-06

申请号：US15465448

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78609 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

公开(公告)号：US09691848B2

公开(公告)日：2017-06-27

申请号：US15334112

申请日：2016-10-25

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/786 ,  H01L29/36 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L21/3065 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/167 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

公开(公告)号：US20170104069A1

公开(公告)日：2017-04-13

申请号：US15382657

申请日：2016-12-17

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/78 ,  H01L29/207 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/205

CPC classification number: H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include forming a modulation doped heterostructure, comprising forming an active portion having a first bandgap and forming a delta doped portion having a second bandgap.

公开(公告)号：US20160190345A1

公开(公告)日：2016-06-30

申请号：US15063371

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/15 ,  H01L29/161

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US20150380557A1

公开(公告)日：2015-12-31

申请号：US14825130

申请日：2015-08-12

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/283 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

Abstract translation: 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。