公开(公告)号：US20170288030A1

公开(公告)日：2017-10-05

申请号：US15353352

申请日：2016-11-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/41741 ,  H01L21/02266 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.

公开(公告)号：US09640633B1

公开(公告)日：2017-05-02

申请号：US14974589

申请日：2015-12-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

发明人： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US20160284607A1

公开(公告)日：2016-09-29

申请号：US14670800

申请日：2015-03-27

申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

摘要： Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

摘要翻译： 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。

公开(公告)号：US20160284602A1

公开(公告)日：2016-09-29

申请号：US14669055

申请日：2015-03-26

申请人： International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L21/823871 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/82385 ,  H01L22/12 ,  H01L22/30

摘要： A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

摘要翻译： 技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。 宏是根据制造工艺制造的。 该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。 执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。 基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。 进行化学机械抛光以除去宏观上的n-p凸块。 先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。

公开(公告)号：US20160181381A1

公开(公告)日：2016-06-23

申请号：US14577431

申请日：2014-12-19

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

发明人： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/41783 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.

摘要翻译： FinFET器件包括半导体鳍片，在鳍片的沟道上延伸的栅极电极和在栅电极的每一侧上的侧壁间隔物。 电介质材料位于所述散热片的底部的每一侧上，其中在散热片的每侧的氧化物材料覆盖在电介质材料上。 在通道区域的每一侧的翅片上形成的凹陷区域由氧化物材料界定。 凸起的源极区域填充凹陷区域并且在栅电极的第一侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。 凸起的漏极区域填充凹陷区域并且在栅电极的第二侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。

公开(公告)号：US20160163850A1

公开(公告)日：2016-06-09

申请号：US14560255

申请日：2014-12-04

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

发明人： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L29/08

CPC分类号： H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7848

摘要： A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

摘要翻译： FinFET晶体管包括具有在沟道区域上延伸的晶体管栅电极的半导体材料的鳍。 从晶体管栅电极的两侧的鳍延伸的第一外延生长材料的引出源区和漏区。 源极和漏极接触开口延伸穿过预金属化电介质材料以到达升高的源极和漏极区域。 第二外延生长材料的源极和漏极接触区域在源极和漏极接触开口的底部处从第一外延生长材料延伸。 金属材料填充源极和漏极接触开口，以分别与源极和漏极接触区域形成源极和漏极接触。 漏极接触区域可以从晶体管栅电极偏移足以在第一外延生长材料的升高的源极区域内提供横向扩散的金属氧化物半导体（LDMOS）配置的偏移距离。

公开(公告)号：US20140367826A1

公开(公告)日：2014-12-18

申请号：US13916669

申请日：2013-06-13

申请人： GLOBALFOUNDRIES, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hsueh-Chung Chen ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Ailian Zhao

IPC分类号： H01L21/768 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01L21/76888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.

摘要翻译： 公开了晶片芯片和芯片的设计方法。 形成具有第一临界尺寸的第一熔丝，并且在芯片的层中形成具有第二临界尺寸的第二熔丝。 可以施加电压以烧尽第一保险丝和第二保险丝中的至少一个。 第一保险丝的第一关键尺寸可以是将第一掩模施加到该层并且将具有第一特性的光施加到掩模。 第二保险丝的第二关键尺寸可以是将第二掩模应用于该层并且将具有第二特性的光施加到掩模。

公开(公告)号：US11869893B2

公开(公告)日：2024-01-09

申请号：US17511647

申请日：2021-10-27

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Chun-Chen Yeh ,  Alexander Reznicek ,  Dechao Guo

IPC分类号： H01L29/786 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L29/165 ,  H01L29/06

CPC分类号： H01L27/0924 ,  H01L21/02532 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545

摘要： Embodiments of the present invention are directed to a method for forming a complementary field effect transistor (CFET) structure having a wrap-around contact. In a non-limiting embodiment of the invention, a complementary nanosheet stack is formed over a substrate. The complementary nanosheet stack includes a first nanosheet and a second nanosheet separated by a dielectric spacer. A first sacrificial layer is formed over a source or drain (S/D) region of the first nanosheet and a second sacrificial layer is formed over a S/D region of the second nanosheet. A conductive gate is formed over channel regions of the first nanosheet and the second nanosheet. After the conductive gate is formed, the first sacrificial layer is replaced with a first wrap-around contact and the second sacrificial layer is replaced with a second wrap-around contact.

公开(公告)号：US20230178559A1

公开(公告)日：2023-06-08

申请号：US17541529

申请日：2021-12-03

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Chun-Chen Yeh ,  Heng Wu ,  Alexander Reznicek

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

CPC分类号： H01L27/1222 ,  H01L27/092 ,  H01L29/42392 ,  H01L27/1262 ,  H01L21/823878

摘要： Fork sheet FET devices with airgap isolation are provided. In one aspect, a fork sheet FET device includes: at least a first nanosheet FET and a second nanosheet FET; and a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar includes an airgap. For instance, the first nanosheet FET and the second nanosheet FET can have nanosheets that extend horizontally on opposite sides of the dielectric pillar. A method of forming a fork sheet FET device having airgap isolation is also provided.

公开(公告)号：US11610101B2

公开(公告)日：2023-03-21

申请号：US16557110

申请日：2019-08-30

申请人： International Business Machines Corporation

发明人： Youngseok Kim ,  Jungwook Choi ,  Seyoung Kim ,  Chun-Chen Yeh

IPC分类号： G06N3/063 ,  G06F17/18 ,  G06F7/58 ,  G06N3/082

摘要： A neuromorphic device includes a plurality of first control lines, a plurality of second control lines and a matrix of resistive processing unit cells. Each resistive processing unit cell is electrically connected with one of the first control lines and one of the second control lines. A given resistive processing unit cell includes a first resistive device and a second resistive device. The first resistive device is a positively weighted resistive device and the second resistive device is a negatively weighted resistive device.